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Note 4 : test condition :'
(1) V
= 5 V, V
DD
DD
(2) Pattern: Mosaic pattern
%
90
10%
(3) Test circuit
CONTROL SIGNAL
(HIGH to LOW)
Note 5: LVDS signal definition
VIN
= Positive differential DATA & CLK Input
+
VIN- = Negative differential DATA & CLK Input
VID = VIN
∆VCM =｜VCM
∆VID =｜VID
VID+ =｜VIH
VID- =｜VIL
VCM = (VIN
VCM+ = (VIH
VCM- = (VIL
µ
rising time = 470
s ± 10%
V
DD
5 V
R1
47K
R2
1K
12V
R3
47K
C3
1uF
– VIN- ,
+
–VCM-｜,
+
–VID-｜,
+
–VIH-｜,
+
–VIL-｜,
+
+VIN-)/2,
+
+VIH-)/2,
+
+VIL-)/2,
+
SPEC NO.
PAGE
μ
Ton=470
s ± 10%
M1
2SK1059
FUSE
M2
2SK1399
C2
10000pF
M T 1 9 0 AW 0 2 V. Y
9/23
V
LCD INPUT)
DD (
C1
1uF
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