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PLC 3 Family Processors
Use the following ladder logic with PLC-3 or PLC-3/10 processors.
This program assumes that your application requires a single BTR
and BTW instruction to pass data between the processor and the
module.
Ladder logic alternates the execution of BTR and BTW instructions.
The processor checks data validity before accepting read data, and
sets one enable bit at a time.
Refer to Figure 6.5 for generalized ladder logic, and to Figure 6.6 for
example ladder logic with entered values.
Figure 6.5
Generalized Ladder Logic for PLC 3 Block Transfer
PLC-3
AC
1
Power
Loss
Bit
BTR
2
DN
EQU
A = BTW cntl
B = BTR cntl
BTW
3
DN
Block Transfer Programming
XOR
A = BTW cntl
B = BTW cntl
R = BTW cntl
BTW
R
G
M
Data
Length
Cntl
BTR
R
G
M
Data
Length
Cntl
Publication 1771 UM006B-EN-P - June 2002
6–7
XOR
A = BTR cntl
B = BTR cntl
R = BTR cntl
LE
DN
ER
LE
DN
ER
15045
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