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Theory of Operation
data and CAMAC cycles are inhibited. Bit 7 of the status bytes
indicates the state of the SRQ line while bits 1-6 are used for
data. The first byte contains X and Q, while the next 4 bytes
contain the LAM status (six slots/byte) starting with slot 1. The
SRQ is cleared when all of the status is read out or when the
8901A receives a serial poll disable command.
TALK MODE
When the 8901A is addressed to Talk (and serial poll mode is
not active) two things occur. First, the 8901A enters the Talker
active state. This causes the direction of the GPIB buffers to be
reversed, since the 8901A must now drive the GPIB bus and it
must disable the acceptor handshake circuit and enable the
source handshake circuit. Secondly, the 8901A starts the execu
tion of a CAMAC cycle. Upon completion of the cycle the ap
propriate number of data bytes are sent to the GPIB Listener
followed by the X and Q response byte which is sent with the
EOI signal asserted.
SOURCE HANDSHAKE
Since the 8901A is in Talk mode, the GPIB handshaking proto
col reverses. That is, the 8901A is now the one to indicate
when data is valid. Three conditions must be met before it can
assert DAV. First, it must be in Talk mode and ATN must be
set false by the GPIB controller. Also it must wait for the GPIB
controller (or Listener) to assert RFD. The last condition is
that the CAMAC data must be latched into the 8901A during
the CAMAC cycle. When all of these conditions have been
met, the 8901A waits an additional 200 nsecs before asserting
DAV to allow time for the data to become stable on the GPIB
bus. When the listening device asserts DAC, DAV is cleared
and a sequencer is clocked to output the next byte. This byte
may be another data byte, or a status byte. If in block mode
the status byte is suppressed, and a new CAMAC cycle is initi
ated instead.
CAMAC CYCLE TIMING
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The CAMAC cycle starts when the 8901A is addressed to Talk
or, if it is in block mode transfer, when the last data byte is
read out. The 8901A asserts the Busy line and enables the
F,A,N,W,C,Z and I drivers. Approximately 500 nsecs later, SI
is asserted for 250 nsecs. At the end of SI, all 24 bits of the
CAMAC data lines, X, and Q are latched in the 8901A. S2 is
asserted 125 nsecs later for 250 nsecs. The cycle is terminated
125 nsecs after S2 goes away. Busy is cleared and all drivers are
disabled.
READ DATA
The sequencer described above determines which data byte is to
read out. The order of the first two bytes may be reversed by
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