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ViewSonic
July 2000 - Version 1.0
Service Manual
VG181
THEORY OF CIRCUIT OPERATION
Output Pin Description (U1)
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Out
! Description _
Output Even Data[23:0] corresponds 'to 24- bit pixel data
for 1-pixel/clock input mode and to the first 24-bit pixel
data for 2-pixel/clock mode.
Output data is synchronized with output data clock(ODCK).
Refer to the TFF and DSTN Signal Mapping application
notes (Sil/AN-0007-A and Sil/AN-0008-A) which tabulates
the relationship between the input data to the transmitter
and output data from the receiver.
A low level on PD or PDO will put the output drivers into a
high impedance (tri-state) mode. A weak internal pull-down
brings each output to ground.
Output Odd Data[23:0] corresponds to the second 24-bit
pixel data for 2-pixels/clock mode.
During 1-pixel/clock mode, these outputs are driven low.
Output data
is synchronized
with output
data clock
(ODCK).
Refer to the TFT and DSTN Signal Mapping application
notes (Sil/AN-0007-A and Sil/AN-0008-A) which tabulates
the relationship between the input data to the transmitter
and output data from the receiver,
A low level on PD or PDO will put the output drivers into a
high impedance (tri-state) mode. A weak internal pull-down
device brings each output to ground.
Output Data Clock. A low level on PD or PDO will put the
output driver into a high impedance
(tri-state) mode. A
weak internal pull-down device brings the output to ground.
Output Data Enable. This signal qualifies the active data
area. A low level on PD or PDO will put the output driver
into a high impedance
(tri-state) mode. A weak internal
pull-down device brings the output to ground.
Horizontal Sync input contro! signal.
Vertical Sync input control signal.
Reserved
Reserved
Reserved
A low level on PD or PDO will put the output drivers
(except CTL1 by PDO) into a high impedance (tri-state)
mode.
A
weak
internal pull-down device
brings each
output to ground.
Page 29
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