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ViewSonic
Service Manual
July 2000 - Version 1.0
VG181
THEORY OF CIRCUIT OPERATION
The operation of PW364
The PW364 is a highly integrated "System on a chip" that interfaces computer
graphics and video inputs in virtually any format to a fixed frequency flat panel
display. An embedded DRAM frame buffer and memory controller perform frame
rate conversion. Computer images from VGA to SXGA resolution input to the chip
can be resized to fit on the target display device. The on-chip microprocessor
incorporates a frame buffer, resizing circuitry and peripheral circuit for frame rate
conversion, image scaling, automatic image optimization, picture in picture, on
screen display and user adjustment.
The intemal block diagram of PW364 is shown below:
PORTA{7: 0)
NMI
» WR
A{19:0}
PORTB{7?:0)
EXTINT
TRRCVR
CS{3:0)
D(15:0)
CPUEN
PORTC (7:0)
WOTEN
(1:0)
RxD
TxD
(1:0)
Internal
Register
Interface
jemory
3
Interfac:
SDRAM
frame
buf far
Cle
Generator
REF
HFBK
CLKIN
,
MCKEXT
DCKEXT
, UCSRC
The interface of PW364 is composed of a microprocessor interface, graphics port
and display port.
Microprocessor interface
When power is present and the power key is pressed, then the reset circuit sets
RESET to a high state and the PW364 to the initial state. After that, the RESET
will transition to a low state and the PW364 starts to work. The microprocessor
executes the programs and configures the internal registers. The execution speed
of the CPU is determined by MCKEXT.
The normal frequency is 125 MHz, but is
40 MHz while in power saving. The D[15:0] , A[19:1]
, RDN
, ROMOEN
and
ROMWEN are used to access external FLASH memory.
The GPiO block incorporates three 8-bit general purpose i/O ports. Each bit in
each port is individually controllable as either input or output.
Page 15
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