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EN 56
8.
QFU2.1E LA
8. IC Data Sheets
This chapter shows the internal block diagrams and pin
configurations of ICs that are drawn as "black boxes" in the
8.1
Diagram
10-2-7 B02A, Tuner-channel decoder
Block diagram
TUNER
TAINP (IF)
IF+
TAINM (IF)
IF-
RFAIN
(RFAGC-MON)
GPIO1 (PWM)
(RFAGC)
TIFAGC
IFAGC
TTUSCL
SCL
TTUSDA
SDA
41MHz or
20.5 MHz
Pinning information
2013-Apr-05
IC Data Sheets
12-bit
ADC
DVB-T2
10-bit
Demodulator
ADC
GPIO
DVB-T
Demodulator
DVB-C
AGC
Demodulator
OSC
PLL
XTALI
XTALO
Figure 8-1 Internal block diagram and pin configuration
electrical diagrams (with the exception of "memory" and "logic"
ICs).
B02A, CXD2834 (IC7KC0)
LDPC/BCH
Stream
Decoder
Processor
TS
RS Decoder
Smoothing
back to
div. table
MPEG
Decoder
TSCLK
TSCLK
TSVALID
TSVALID
TSIF
TSSYNC
TSSYNC
TSDATA7-0
TSDATA7-0
SCL
SCL
I
2
C IF
SDA
SDA
19220_025_120227.eps
120227
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