Uut Interface Section; Timing Section - Fluke 9000A-8080 Instruction Manual

8080
4-4. UUT Interface Section
The UUT Interface Section, shown m Figure 4-1, include the following
elements:
• Data and address buffers
• Protection circuits for signal lines
• Logic level detection circuits for data, address, status and control lines
The data and address buffers are enabled to connect the microprocessor to the
UUT, or disabled to isolate the microprocessor from the UUT. Control of the
buffers is maintained by the timing section.
Each line to the U UT contains a protection circuit. A protection circuit consists
of a 100-ohm series-resistor and clipping diodes. This circuit prevents over
voltage conditions from damaging pod components.
Each line to the U UT contains a dectection circuit. A detection circuit consists of
a latch connected to the UUT side of the 100-ohm protection resistor. The latch
senses the level at the UUT side of the protection circuit, and at the conclusion of
each UUT operation, stores the level of the UUT line. Each latch is then
individually addressed and read by the Processor Section. Their contents are
then compared with the desired results as a means of detecting UUT bus faults.
4-5. Timing Section
The primary function of the timing section is to cause the microprocessor to
work with either the Processor Section or the UUT Interface Section at a time
pre-determined by the microprocessor itself. Causing the microprocessor to
work with one section or the other as required during the execution of
troubleshooter commands, permits the use of only one microprocessor in the
pod.
The Timing Section of the pod, shown in Figure 4-1, consists of an interval timer
and an arrangement of timing circuits. The interval timer, preset by the
microprocessor, determines the time at which the microprocessor switches from
addressing the Processor Section (RAM, ROM and l/ 0) to addressing the U UT
Interface Section (and UUT). This timing is critical, since any attempt by the
microprocessor to address the Processor Section with addresses meant for the
UUT, or vice versa, would result in improper operation.
In their reset state, the timing circuits cause the microprocessor to operate as a
part of the Processor Section, which includes an I/ 0 port to the troubleshooter.
When the troubleshooter issues a pod command which calls for a UUT read or
write operation, the microprocessor sets the interval timer to a specific value.
The value set on the interval timer corresponds to the time needed by the
Processor Section to prepare for command execution prior to actually
addressing the U UT.
4-4