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2.
Individual Block Descriptions
(1) Key Matrix
Six
of the
seven
operation
push-buttons
on
the front panel of the video disc player (the
CX
push-button
being
the
exception)
con-
stitute a key matrix.
Six separate commands
can
be sent
to the transmitter
(2) by push-
button operation.
[c
) Transmitter
The
output
from
the
remote
control
trans-
mitter
IC (M50110CP)
is obtained
by push-
button
selection
of the output
from
the IC
scan
signal generator. and subsequent
conver-
sion of the returning signal into a 10-bit serial
PCM
encoded
signal. Although
this IC output
signal is obtained in the form of a 10-bit PCM
code
amplitude
modulated
by
the
38kHz
carrier, the 38kHz
component
is removed bya
detector circuit following the IC.
(3) IRAB
This
stage
receives
infrared
signals from
the
remote control section which is equipped with
the same
kind of transmitter IC as described
in (2) above.
Hence, the infrared signal from
the remote control section following reception
and
photoelectric
conversion
in
the
IRAB
photo-detector
is detected,
shaped,
and
con-
verted into a 10-bit serial PCM encoded signal
which is subsequently passed to the next stage.
(4) Front panel key priority circuit
This circuit ensures priority of the front panel
push-button
input
signals
over
the
remote
control unit key input signals. By pushing any
of
the
player
front
panel
operation
push-
buttons,
the gate is switched
by utilizing the
oscillator
action
of the
IC described
in (2)
above.
(5) Receiver
This stage contains the remote
control recep-
tion IC M50117CP). 10-bit serial PCM encoded
signals
obtained
by
pressing
the
player
or
remote
control
operation
push-buttons
are
converted
to
5-bit
parallel
binary
encoded
signals before being passed on to the data pro-
cessor.
PR-8210-A
(6) PLL
Consisting of a phase comparator (TC5081 AP),
a low-pass filter, and a discrete VCO,
the PLL
stage generates
3.02MHz
clock signals for the
data
processor.
The
1/192
divider
circuit in
the data processor
generates an HB signal of
the same repetition frequency as the horizontal
synchronizing signal, and applies the signal to
the phase
comparator
input. The phase com-
parator
clock
serves
as
the
character
dot
reference
for
frame
numbers
etc,
it being
necessary for the display of this data in the TV
screen
to be synchronized
accurately
with the
horizontal
synchronizing
signal.
For
this
reason,
this PLL
stage is designed
to ensure
synchronization with the PB H signal from the
VSOP.
(7) Data gate
Each type of data detected from the playback
video signal is applied to the data gate where
the
vertical
and
horizontal
synchronizing
signals serve as reference signals. Only data in
lines 16 and 18 is extracted and subsequently
passed to the data processor.
(8) Slider position detector
The DC voltage from the slider pot is applied
to two separate comparators as slider position
data, this data being used to detect each inside
and outside limit position.
(9) Reset control circuit
The CPU is protected against power reductions
by means
of a "reset control" which involves
detection of drops in the Vpp voltage.
(10) Spindle rotation detection
The SPDL motor FG output is integrated and
then passed to a comparator as motor rotation
data, thereby
fulfilling one of the conditions
for opening the player lid.
29
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