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Fig. 9-1
9.3 LCD Assembly
9.3.1 Specifications
LCD:
esolution
640x480 dots
pI
to)
1
[Duy
«10240
|
| Type
FTN reflective
= |
type
|
|
LCD
|
| Dot Size
0.24(W)x0.24
|
H
257(W)x158.5(H)x
9.5(D
180 (W) x 133
H
| Power supply VDD
DD
Ph
ro rrr
hh
ne
emcee
O
fo.
Outline Dimension
Effective View Area
9.3.2 Theory of the LCD operation
The following figure is the block diagram of the
LCD module:
The LCD driver is 80 bits LSI, consisting of shift
registers, latch circuits and LCD driver circuits.
Display data which are externally divided into data
for each row (640 dots) will be sequentially
transferred in the form of 4-bit parallel data through
shift registers by Clock Signal CP2 from the left top
of the display face.
When data of one row (640 dots) have been input,
they will be latched in the form of parallel data for
640 lines of signal electrodes by Latch Signal CP1.
Then the corresponding drive signal will be
transmitted to the 640 lines of column electrodes of
the LCD panel by the LCD drive circuits.
At this time, scan start-up signal S has been
transferred from the scan signal driver to the ist
row of scan electrodes, and the contents of the
data signals are displayed on the 1st rows of upper
and lower half of the display face according to the
combinations of voltages applied to the scan and
signal electrodes of the LCD.
CS 55 863
4&5 689 Al4&
While the 1st rows of data are being displayed, the
2nd rows of data are entered. When 640 dots of
data have been transferred, then latched on the
falling edge of CP1 clock, the display face
proceeds to the 2nd rows of display.
Such data input will be repeated up to the 240th
row of each display segment, from upper to lower
rows, to complete one frame of display by time
sharing method. Then data input proceeds to the
next display face.
Scan start-up Signal S generates scan signal to
drive horizontal electrodes.
Since DC voltage, if applied to LCD panel, causes
chemical reaction which will deteriorate LCD panel,
drive waveform shall be inverted at every display
frame to prevent the generation of such DC
voltage. Control Signal M plays such a role.
Because of the characteristics of the CMOS driver
LSI, the power consumption of the unit goes up as
the operating frequency CP2 increases. Thus the
driver LSI applies the system of transferring 4-bit
parallel data through the 4 lines of shift registers to
reduce the data transfer speed CP2. Thanks to the
LSI, the power consumption of the unit will be
minimized.
In this circuit configuation, 4-bit display data shall
be therefore input to data input pins of DU0-3
(upper display segment) and DLO-3 (lower display
segment.)
Furthermore the LCD unit adopts bus line system
for data input to minimize the power consumption.
In this system data input terminal of each driver LSI
is activated only when relevant data input is fed.
Data input for column electrodes of both the upper
and the lower display segment and chip select of
driver LSI are made as follows:
The driver LSI at the left end of the display face is
first selected, and the adjacent driver LSI of the
right side is selected when 80 dots data (20 CP2)
is fed. This process is sequentially continued until
data is fed to the driver L at the right end of the
display face.
This process is simultaneously followed at the
column driver LSI of both the upper and the lower
display segments. Thus data input for both the
upper and the lower display segments must be fed
through 4 -bit bus line sequentially from the left end
of display face.
Since this graphic display unit contains no refresh
RAM, it requires data and timing pulse inputs even
for static display.
Frame cycle of 11.7 ms min. or frame frequency of
85 Hz max. will demonstrate optimum display
quality in terms of flicker an 'shadowing'. LCD unit
functions at the minimum frame cycle of 8 ms
(maximum frame frenquency of 125 Hz).
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