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XVDD
|
Crystal oscillator power supply pin.
a
a
en
47
48
Pin to which external 16.9344 MHz crystal oscillator is connected.
| 47
SBSY
| o | Subcode block sync signal output pin.
EFLG
C1, C2, single and dual correction monitoring pin.
PW
EO
Subcode P, Q, R, S, T, U and W output pin.
SFSY
lo | Subcode frame sync signal output pin. Falls down when subcode enters standby.
49
50
Subcode read clock input pin. Schmidt input. (Be sure to connected to 0V when not in
SBCK
I
53
Subcode Q output standby output pin.
Read/write control input pin. Schmidt input
SQOUT
| o | Subcode Q output pin.
5
use.)
Pin outputting the 7.35 kHz sync signal which is generated by dividing frequency of
52
;
crystal oscillator.
a a a
*
57
Command input read clock or subcode read input clock from SQOUT pin
LC78622 reset input pin. Set this pin to L once when the main power is turned on.
58
in.
59
TST11
| o | Test signal output pin. Use this pin as open (normally L output)
> i 16.9344 MHz output pin.
.
4.2336 MHz output pin.
Test signal input pin with built-in pull-down resistor. Be sure to connect to OV.
Ww
R
RE
1
RQ
WC
56
COIN
I
Command input pin from microprocessor
CK
Ss
6M
4.2M
Tests.
|
|
6
. 62
63
Chip select signal input pin with built-in pull-down resistor. Be sure to connect to 0V
while it is not controlling.
64
'
TESTI
Test signal input pin without built-in pull-down resistor. Be sure to connect to OV.
Note:
The same potential must be applied to the respective power supply terminals. (VDD, VVDD, LVDD, RVDD, XVDD)
17
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