Advertisement
Pin from which TES signal is output to DSP.
SLOF
Sled servo off control input pin.
39, 40
CV-—, CV+
CLV error signal input pin from DSP.
_
Sh)
ones
RF gain setting and EFM signal 3T compensation constant setting pin together with
Pin No.
"High Frequency Level" is used to judge whether the main beam position is on top of
A
8
fe if
RFSM pin.
"Slice Level Control" is the output pin which controls the RF signal data slice level by
Ww —_
SLC
DSP.
44
SLI
Input pin which control the data slice level by the DSP.
5
DGND
—_
Digital system GND.
6
FSC
oO
Output pin to which external focus search smoothing capacitor is connected.
7
TBC
I
"Tracking Balance Control" EF balance variable range setting pin.
=
No connection.
DEF
oO
Disc defect detector output pin.
| 50
Reference clock input pin. 4.23 MHz of the DSP is input.
pax
ai
a ee
el
ee OO
po
| acer eid peat
a
"Focus Search Select" focus search mode (+ search/+ search) select pin.
VCC2
Servo system and digital system Vcc pin
REFIT
Pin to which external bypass capacitor for reference voltage is connected.
Reference voltage output pin
LF2
Disc defect detector time constant setting pin.
|
PH1
Pin to which external capacitor for RF signal peak holding is connected
Po [acetate
pa [veo [= [rrommvenn
SSCSCSC~—"SCSCS*S
Ww oo
15
Advertisement
