Hardware Guide; Q7 Implementation - Cherry RINGNECK SOM-PX30-uQ7 User Manual

12 Hardware Guide

This Hardware Guide provides information about the features, connectors and signals available on the RING-
NECK SOM-PX30-uQ7 module.

12.1 Q7 Implementation

Q7 has mandatory and optional features.
SOM-PX30-uQ7 module compared to the minimum ARM/RISC based and maximum configuration according
to the Q7 standard.
System I/O Interface
PCI Express lanes
Serial ATA channels
USB 2.0 ports
USB 3.0 ports
LVDS channels
Embedded DisplayPort
MIPI-CSI
HDMI
High Definition Audio / AC'97 / I2S
Ethernet 10/100/Gigabit
UART
GPIO
Secure Digital I/O
System Management Bus
I²C Bus
SPI Bus
CAN Bus
Watchdog Trigger
Power Button
Power Good
Reset Button
LID Button
Sleep Button
Suspend to RAM (S3 mode)
Wake
Battery low alarm
Thermal control
FAN control
Note: The RINGNECK SOM-PX30-uQ7 module is available in different variants. This document describes the
maximum configuration. For details about orderable variants please refer to the order-code document.
Note: Not all interfaces are available at the same time as they might conflict with others. E.g. it is not possible
to have LVDS channels and MIPI-DSI at the same time.
v1.3.1
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Following table shows the feature set of the RINGNECK
Q7 Minimum RINGNECK SOM-PX30-uQ7
0 0
0 0
1 4
0 0
0 1
0 0
0 1
0 0
0 1
0 1x 100Mbps
0 1 (+1 shared with GPIO)
0 8
0 1
0 0
1 3
0 1
0 1
1 1
1 1
1 1
1 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
Q7 Maximum
4
2
8
3
2
1
2
1
1
1x Gigabit
1
8
1
1
4
1
1
1
1
1
1
1
1
1
1
1
1
1