Pioneer DVL-90 Service Manual page 110

DVL-90, DVL-700
[No.|PinName| VO | PinFunction No. [Pin Name] VO] Pin Function
Composite blanking output and clock reference PANTIE ' ;
VBLK 0 | signal Selectable by mode setting 77 |ANCK Clock signal at ancillary data output
| 42 |vCBF | O [Colorburst insertion position signal =| Color burst insertion position signal = sf 78 [GND =| - |Groundpn ss
VLSW jo Line switch (at PAL used) }79 |OREG | 0 — signal when stream input via the host
a4 | ws | Vertical sync. signal output Also selectable to DAGK Acknowledge signal when stream input via the
vertical reset signal by mode setting. host path.
Horizontal syne. signal output : :
45 |VHS Selectable to composite sync. signal or A44E sr aalnag caso gaa : si iebes sae
horizontal reset signal by mode register setting P , '
se |
}46 {GND =| - |Groundpin = ss—s—s—sSsSi 82 FCK_AU || [Auli sampling clock input
Host interface mode selection
VDCo HMOT HMOT : When set to H, it becomes bus mode of
68 system.
Communicate the end of bus cycle to the host
Enable signal when the host is wrote
5 fal Input WR signal in the 78k bus mode.
ba vbc4 }g0 |HCS | I | Chip select signal of active *L"
Video data clock output
De Frequency outpue to 27MHz and 13.5MHz. [ss fvoo | - | Power supply pin
Interrupt request signal to the host
. VDC1 HIRQ This pin becomes active when accapting the
Video chroma Cb and Cr output interrupt. This pin is tri-state output.
CPU in the 68k mode.
Input R/W signal in the 68k bus mode.
Address latch enable signal
Video chroma Cb and Cr output HALE anu When address and data is not multiplexed, pull-
up to "H'.
These pins output Cb and Cr video signal at 16 Tri-state ready output
bit mode.
vpce ee 87 |HRDY
Use for Wait signal in the 78k0 mode.
Enable signal when the host is readed
Ground pin Input RD signal in the 78k bus mode.
Input data strobe signal in the 68k bus mode.
These pins output Cb and Cr video signal at 16
li Video data output
| 60 |VDY1 | Output Y data only at 16 bit mode.
61 |vDY2 Neen Cb, Y, Cr and Y video format at 8 bit
mode.
ees
VDY4
Video data output
}65 |VDY5 | Output Y data oly at 16 bit mode.
VDY Output Cb, Y, Cr and Y video format at 8 bit
rerpor | fre rs fia
Ke i Sn CT
pros [Hae |
Audio data clock output soot |
LR svitching signal fio7|vob__| [Powersuppiypin
Master clock for audio HAA
Outputs same frequency as CK_AU pin
Emphasis output When existing the emphasis
in conformity to 50 / 15us, outputs °"H".
Host address bus input
This address bus is able to multipled to HD7-0
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go
i
wd
BCK
ALRCK
a
Host address bus input
This address bus is able to multipled to HD7-0
Emphasis output When existing the emphasis
in conformity to ITU-TJ.71, outputs "H".
Ancillary strobe signal 41 |HA7 |
Ancillary data output
3