Advertisement
PC— 1425
| Out | Memory chip enable.
O
Out
SIO [RR] . Sending of receive
enabled from this end. (buffered by
gate alley)
Out
St!O [ER]. Goes high by the execu-
tion of OPEN command.
Low during
stand by (buffered by gate alley)
ut
~ Out
'Data output to option unit
Data output to option unit
8
N
f=?)
B
ml NO
O
ba a
—
*
P-type open drain output
Al4
a
9
C$1
ymbol
af
55
cS3Nn
Or
| OQ joo
EE
EE
am
ol
Pip>|
2
o|°is
34
A9
CS4N
i
R/W
eaipeee
___4_
yx OUTS
D5
KO6
D2
a
2
KO8
pip
20
Ko?2
48
EXT4
*
47
Data
EXT3
latch
Ad
EXT2
2k
2
EXT1
*
Write clock, normaily high.
Address bus
Address bus
Power supply (©)
Address bus
(
Address bus
SIO [ER] output from the CPU that
goes high with OPEN command, which
is buffered in the gate array.
SIO [RR] output from the CPU that
for receive enable, which is buffered
in the gate array.
transmit data.
Memory enable
07
Out
Key strobe output
Ou
Ou
Ou
Ou
a
Out
|. Key strobe output
Out
Out
ROM A714 signal
~
G)
lz
-|0
eee
ne
N
> ol
FO1
O
= — > te)
TI
NO
04
— o
a
"Tl
3
~~.
oO
Cc
oo
DO
a
ALA
Hii
tii
=
NEN
EN
Bee
A O a)
t
t
t
AQ
D2
|
BNK3
t
Data
39
latch
BNK2
28g
BNK1
<a)
~
LALA
O1O|O
OO}
als
G) 2
f
A
O o
Uf
oO ~
INI
Input
port
NO | Go Zzi2
CS1
, ROM A'15 signai
| — | ROM A16 signal
Out
S10 [SD] and FO4 buffered transmit
data
Out
SIO[RS] and iB2 buffered send request
Out
| SIO [RR] and FO2 buffered ready
N) ~
ww
2i2 A\ A WW) N
Advertisement
