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AKM AK4951A Manual

24bit stereo codec with mic/hp/spk-amp
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The AK4951A is a low power 24-bit stereo CODEC with a microphone, headphone and speaker
amplifiers.
The AK4951A supports sampling frequency from 8kHz to 48kHz. It is suitable for a wide range of
application from speech signal processing for narrowband, wideband and super wideband to sound
signal processing for audio band.
The input circuits include a microphone amplifier, an automatic wind noise reduction filter of the
proprietary algorithms and a high performance digital ALC (automatic level control) circuit, therefore the
AK4951A can record with high-quality sound regardless of whether indoors or outdoors. In addition, the
output circuits include a cap-less headphone amplifier with a negative voltage generated by charge pump
circuit and a speaker amplifier with 1W output power. It is suitable for various products as well as portable
applications with recording/playback function.
The AK4951A are available in a small 32-pin QFN (4mm x 4mm, 0.4mm pitch) package saving mounting
area on the board.
Application:
 IP Camera
 Digital Camera
 IC Recorder
 Tablet
 Wireless Headphone
 Headset
1.
016001936-E-00
Arrow.com.
Downloaded from
24bit Stereo CODEC with MIC/HP/SPK-AMP
Recording Functions
 Analog Input: 3 Stereo Single-ended inputs with Selectors
 Microphone Amplifier: +30dB ~ 0dB, 3dB Step
 Microphone Power Supply: 2.0V or 2.4V, Noise Level= 108dBV
 Digital ALC (Automatic Level Control)
- Setting Range: +36dB  52.5dB, 0.375dB Step & Mute
 ADC Performance: S/(N+D): 83dB, DR, S/N: 88dB (MIC-Amp=+18dB)
S/(N+D): 85dB, DR, S/N: 96dB (MIC-Amp=0dB)
 Microphone Sensitivity Correction
 Automatic Wind Noise Reduction Filter
Selectable voice peak detection mode
 5-Band Notch Filter: Include Dynamic Gain Control
 Stereo Separation Emphasis Circuit
 Digital Microphone Interface

1. General Description

2. Features

- 1 -
[AK4951A]
AK4951A
2016/03

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Summary of Contents for AKM AK4951A

  • Page 1: General Description

    The AK4951A is a low power 24-bit stereo CODEC with a microphone, headphone and speaker amplifiers. The AK4951A supports sampling frequency from 8kHz to 48kHz. It is suitable for a wide range of application from speech signal processing for narrowband, wideband and super wideband to sound signal processing for audio band.
  • Page 2 [AK4951A] Playback Functions  Digital ALC (Automatic Level Control) - Setting Range: +36dB ~ 52.5dB, 0.375dB Step & Mute  Sidetone Mixer & Volume Control (0dB ~ 18dB, 6dB Step)  Digital Volume Control - +12dB ~ 89.5dB, 0.5dB Step & Mute ...

  • Page 3: Table Of Contents

    [AK4951A] 3. Table of Contents General Description ..........................1 Features............................... 1 Table of Contents ..........................3 Block Diagram and Functions ......................5 ■ Block Diagram ............................ 5 ■ Comparison Table to AK4951 ......................6 Pin Configurations and Functions ....................... 7 ■...
  • Page 4 [AK4951A] ■ Speaker Output (SPP/SPN pins, LOSEL bit = “0”) ................62 ■ Thermal Shutdown Function ......................63 ■ Stereo Line Output (LOUT/ROUT pin, LOSEL bit = “1”) ..............64 ■ Regulator Block ..........................66 ■ Serial Control Interface ........................67 ■...

  • Page 5: Block Diagram And Functions

    [AK4951A] 4. Block Diagram and Functions ■ Block Diagram VCOM VSS1 REGFIL AVDD DVDD TVDD VSS2 PMMP MPWR2 MIC Power MPWR1 AVDD Supply Analog Block 2.3V Digital Core, Headphone-Amp MIC-Power, Control PMADL Charge-pump Register Internal LIN1 PMADL or PMADR RIN1...

  • Page 6: Comparison Table To Ak4951

    Register Name Device Information REV3 REV2 REV1 REV0 DVN3 DVN2 DVN1 DVN0 REV3-0: Device Revision ID (Read operation only.) 1100: AK4951 1101: AK4951A 016001936-E-00 2016/03 - 6 - Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Downloaded from Downloaded from Downloaded from...

  • Page 7: Pin Configurations And Functions

    [AK4951A] 5. Pin Configurations and Functions ■ Pin Layout VSS2 TVDD MCKI BICK AVDD AK4951AEN LRCK VSS1 SDTO Top View VCOM SDTI REGFIL RIN3/BEEP Figure 2. Pin Layout 016001936-E-00 2016/03 - 7 - Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 8: Pin/Function

    [AK4951A] ■ PIN/FUNCTION Pin Name Function LIN3 Lch Analog Input 3 pin RIN2 Rch Analog Input 2 Pin LIN2 Lch Analog Input 2 pin MPWR2 MIC Power Supply 2 Pin MPWR1 MIC Power Supply 1 Pin (DMIC bit = “0”: default)

  • Page 9: Handling Of Unused Pin

    Ambient) is 42C/W at JESD51-9 (2p2s). When Pd =840mW and the θja is 42C/W, the junction temperature does not exceed 125C. In this case, the AK4951A will not be damaged by its internal power dissipation. Therefore, the AK4951A should be used in the condition of θja ≤ 42C/W.

  • Page 10: Recommended Operating Conditions

    SVDD can be powered ON/OFF. The PDN pin must be set to “H” after all power supplies are ON, when the AK4951A is powered-up from power-down state. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. 016001936-E-00...

  • Page 11: Electrical Characteristics

    [AK4951A] 8. Electrical Characteristics ■ Analog Characteristics (Ta=25C; AVDD=SVDD=3.3V, TVDD=DVDD=1.8V; VSS1=VSS2=VSS3=0V; fs=48kHz, BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Bandwidth=20Hz  20kHz; unless otherwise specified) Parameter Min. Typ. Max. Unit MIC Amplifier: LIN1, RIN1, LIN2, RIN2, LIN3, RIN3 pins Input Resistance k...
  • Page 12 [AK4951A] Parameter Min. Typ. Max. Unit DAC Characteristics: Resolution Bits Headphone-Amp Characteristics: DAC → HPL, HPR pins, ALC=OFF, IVOL=DVOL= 0dB, R =16 Output Voltage (0dBFS) 1.44 1.60 1.76 =16Ω S/(N+D) =10kΩ S/N (A-weighted) Interchannel Isolation Interchannel Gain Mismatch Output Offset Voltage ...
  • Page 13 [AK4951A] Parameter Min. Typ. Max. Unit Mono Input: BEEP pin (PMBP bit =“1”, BPVCM bit = “0”, BPLVL3-0 bits = “0000”) Input Resistance k Maximum Input Voltage (Note 1.54 Gain 1 BEEP pin → HPL, HPR pins BEEP pin → SPP/SPN pins (Note SPKG1-0 bits = “00”...

  • Page 14: Power Consumption On Each Operation Mode

    [AK4951A] ■ Power Consumption on Each Operation Mode Conditions: Ta=25C; AVDD=SVDD=3.3V, TVDD=DVDD=1.8V; VSS1=VSS2=VSS3=0V; fs=48kHz, Programmable Filter=OFF, External Slave Mode, BICK=64fs; LIN1/RIN1 input = No signal; SDTI input = No data; Headphone & Speaker outputs = No load. Table 1. Power Consumption on Each Operation Mode (typ)

  • Page 15: Filter Characteristics

    [AK4951A] ■ Filter Characteristics (Ta =25C; fs=48kHz; AVDD=2.8  3.5V, SVDD=1.8 ~ 5.5V, DVDD = 1.6 ~ 1.98V, TVDD = 1.6 or (DVDD-0.2) 3.5V) Parameter Symbol Min. Typ. Max. Unit ADC Digital Filter (Decimation LPF): 0.16dB Passband (Note 18.8 0.66dB 21.1...

  • Page 16: Dc Characteristics

    [AK4951A] ■ DC Characteristics (Ta =25C; fs=48kHz; AVDD=2.8 ~ 3.5V, SVDD= 1.8 ~ 5.5V, DVDD = 1.6 ~ 1.98V, TVDD = 1.6 or (DVDD-0.2)  3.5V) Parameter Symbol Min. Typ. Max. Unit Audio Interface & Serial µP Interface (CDTIO/CAD0, CSN/SDA, CCLK/SCL, I2C, PDN, BICK, LRCK, SDTI, MCKI pins) (TVDD ≥...

  • Page 17: Switching Characteristics

    [AK4951A] ■ Switching Characteristics (Ta=25C; fs=48kHz; C =20pF; AVDD=2.83.5V, SVDD=1.8~5.5V, DVDD=1.6~1.98V, TVDD=1.6 or (DVDD-0.2)3.5V) Parameter Symbol Min. Typ. Max. Unit PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing PLL3-0 bits = “0100” Frequency fCLK 11.2896 PLL3-0 bits = “0101”...
  • Page 18 [AK4951A] Parameter Symbol Min. Typ. Max. Unit External Master Mode MCKI Input Timing Frequency 256fs fCLK 2.048 12.288 384fs fCLK 3.072 18.432 512fs fCLK 4.096 24.576 1024fs fCLK 8.192 24.576 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK Output Timing CM1-0 bits = “00”...
  • Page 19 Note 28. It is the time of 10% potential change of the CDTIO pin when R Note 29. The AK4951A can be reset by the PDN pin = “L”. The PDN pin must be held “L” for more than 200ns for a certain reset. The AK4951A is not reset by the “L” pulse less than 50ns.

  • Page 20: Timing Diagram

    [AK4951A] ■ Timing Diagram 1/fCLK MCKI tCLKH tCLKL 1/fs 50%TVDD LRCK tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 1/fBCK BICK 50%TVDD tBCKH tBCKL Duty = tBCKH x fBCK x 100 tBCKL x fBCK x 100 Figure 3.
  • Page 21 [AK4951A] MCKI 1/fs LRCK tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 1/fBCK BICK tBCKH tBCKL Figure 5. Clock Timing (PLL Slave mode) 1/fCLK MCKI tCLKH tCLKL 1/fs LRCK Duty = tLRCKH x fs x 100...
  • Page 22 [AK4951A] tSCK 65%AVDD DMCLK 50%AVDD 35%AVDD tSCKL tSRise tSFall dSCK = 100 x tSCKL / tSCK Figure 8. DMCLK Clock Timing 65%AVDD DMCLK 35%AVDD tDSDS tDSDH VIH2 DMDAT VIL2 Figure 9. Audio Interface Timing (DCLKP bit = “1”) 65%AVDD DMCLK...
  • Page 23 [AK4951A] tAPD tRPD Figure 12. Power Down & Reset Timing 1 PMADL/R bit PMDML/R bit tPDV SDTO 50%TVDD Figure 13. Power Down & Reset Timing 2 PMVCM bit tRVCM 1.15V VCOM pin Figure 14. VCOM Rising Timing 016001936-E-00 2016/03 - 23 - Arrow.com.

  • Page 24: Functional Descriptions

    “1”. When the AK4951A is in master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The LRCK and BICK pins of the AK4951A must be pulled-down or pulled-up by a resistor (about 100k) externally to avoid the floating state.

  • Page 25: Pll Mode

    When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) circuit generates a clock that is selected by PLL3-0 and FS3-0 bits. The PLL lock times, when the AK4951A is supplied stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or the sampling frequency is changed, are shown in...
  • Page 26 Note 34 Sampling frequency that differs from sampling frequency of mode name Note 33. These values are rounded off to six decimal places. Note 34. The AK4951A must be in EXT master mode when selecting this mode. 016001936-E-00 2016/03 - 26 - Arrow.com.
  • Page 27 Note 33. These values are rounded off to six decimal places. Note 34. The AK4951A must be in EXT master mode when selecting this mode. 3) Setting of sampling frequency in PLL Mode (PLL reference clock input pin = BICK pin) When PLL reference clock input is BICK pin, the sampling frequency is selected by FS3-0 bits as defined in Table 8.

  • Page 28: Pll Unlock State

    [AK4951A] ■ PLL Unlock State In this mode, LRCK and BICK pins go to “L” until the PLL goes to lock state after PMPLL bit = “0” → “1” (Table After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state after a period of 1/fs.

  • Page 29: Pll Master Mode (Pmpll Bit = "1", M/S Bit = "1")

    When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 16MHz, 24MHz or 27MHz) is input to the MCKI pin, the internal PLL circuit generates BICK and LRCK clocks. When the state of AK4951A is ADC power-down or Loopback mode, the output of BICK, LRCK and SDTO pins can be stopped by CKOFF bit.

  • Page 30: Ext Slave Mode (Pmpll Bit = "0", M/S Bit = "0")

    EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4951A becomes EXT mode. Master clock can be input to the internal ADC and DAC directly from the MCKI pin without internal PLL circuit operation. This mode is compatible with I/F of a normal audio CODEC.

  • Page 31: Ext Master Mode (Pmpll Bit = "0", M/S Bit = "1")

    EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4951A becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input to the internal ADC and DAC directly from the MCKI pin without the internal PLL circuit operation.

  • Page 32: System Reset

    System Reset Upon power-up, the AK4951A must be reset by bringing the PDN pin = “L”. This reset is released when a dummy command is input after the PDN pin = “H”. This ensures that all internal registers reset to their initial value.
  • Page 33 [AK4951A] The ADC starts an initialization cycle if the one of PMADL or PMADR is set to “1” when both of the PMADL and PMADR bits are “0”. The initialization cycle is set by ADRST1-0 bits (Table 18). During the initialization cycle, the ADC digital data outputs of both channels are forced to “0”...

  • Page 34: Audio Interface Format

    MSB first, 2’s complement format. Audio interface formats are supported in both master and slave modes. LRCK and BICK are output from the AK4951A in master mode, but must be input to the AK4951A in slave mode. The SDTO is clocked out on the falling edge (“”) of BICK and the SDTI is latched on the rising edge (“”) of BICK.
  • Page 35 [AK4951A] LRCK BCLK(64fs) SDTO(o) 23 22 23 22 SDTI(i) Don’t Care Don’t Care 23:MSB, 0:LSB Lch Data Rch Data Figure 23. Mode 2 Timing LRCK BICK(32fs) SDTO(o) 23 22 23 22 16 15 14 13 12 16 15 14 13 12...

  • Page 36: Adc Mono/Stereo Mode

    ■ MIC/LINE Input Selector The AK4951A has an input selector. INL1-0 and INR1-0 bits select LIN1/LIN2/LIN3 and RIN1/RIN2/RIN3, respectively. When DMIC bit = “1”, digital microphone input is selected regardless of INL1-0 and INR1-0 bits. RIN3 pin is shared with BEEP pin. When PMBP bit = “0”, RIN3 pin can be selected.

  • Page 37: Microphone Gain Amplifier

    Microphone Gain Amplifier The AK4951A has a gain amplifier for microphone input. It is powered-up by PMADL/R bit = “1”. The gain of MIC-Amp is selected by the MGAIN3-0 bits. The typical input impedance is 30k. A click noise may occur if the MIC-Amp gain is changed when both MIC-Amp and ADC (PMADL/R bits = “1”) are powered...

  • Page 38: Digital Microphone

    Figure 27 show stereo/mono connection examples. The DMCLK clock is input to a digital microphone from the AK4951A. The digital microphone outputs 1bit data, which is generated by Modulator using DMCLK clock, to the DMDAT pin. PMDML/R bits control power up/down of the digital block (Decimation Filter and Digital Filter). (PMADL/PMADR bits settings do not affect the digital microphone power management.
  • Page 39 DMCLK pin= “L”. The DMCLK pin only supports 64fs. It outputs “L” when DCLKE bit = “0”, and outputs 64fs when DCLKE bit = “1”. In this case, necessary clocks must be supplied to the AK4951A for ADC operation. The output data through “the Decimation and Digital Filters” is 24bit full scale when the 1bit data density is 0%~100%.

  • Page 40: Digital Block

    [AK4951A] ■ Digital Block The digital block consists of the blocks shown in Figure 30. Recording path and playback path is selected by setting ADCPF bit, PFDAC1-0 bits and PFSDO bit (Figure 31 Figure Table 26). PMADL/R bit SDTI 1st Order...
  • Page 41 [AK4951A] Table 26. Recording Playback Mode Example ADCPF PFDAC1-0 PFSDO Mode Example Figure bits Recording Mode 1 & Playback Mode 2 Figure 31 (default) Recording Mode 2 & Playback Mode 1 Figure 32 Recording Mode 2 & Playback Mode 2...

  • Page 42: Digital Hpf1

    78.9Hz 236.8Hz ■ Microphone Sensitivity Correction The AK4951A has linear microphone sensitivity correction function controlled by MGL/R7-0 bits. MGL/R7-0 bits must be set when PMADL/R bits = “0” or PMPFIL bit = “0”. Table 28. Microphone Sensitivity Correction MGL7-0 bits...

  • Page 43: Automatic Wind Noise Reduction Filter

    Automatic Wind Noise Reduction Filter The AK4951A has an automatic wind noise reduction filter that is controlled by AHPF bit. The automatic wind noise reduction filter is ON when AHPF bit = “1”. It attenuates the wind noise when detecting a wind noise and adjusts the attenuation level dynamically.

  • Page 44: Digital Programmable Filter Circuit

    [AK4951A] ■ Digital Programmable Filter Circuit (1) High Pass Filter (HPF2) This is composed 1st order HPF. The coefficient of HPF is set by F1A13-0 bits and F1B13-0 bits. HPF bit controls ON/OFF of the HPF2. When the HPF2 is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when PMPFIL bit = “0”...
  • Page 45 [AK4951A] (3) Stereo Separation Emphasis Filter (FIL3) The FIL3 is used to emphasize the stereo separation of stereo microphone recording data and playback data. F3A13-0 bits and F3B13-0 bits set the filter coefficients of the FIL3. When F3AS bit = “0”, the FIL3 performs as a High Pass Filter (HPF), and it performs as a Low Pass Filter (LPF) when F3AS bit = “1”.
  • Page 46 [AK4951A] (4) Gain Compensation (EQ0) Gain compensation is used to compensate the frequency response and the gain that is changed by the stereo separation emphasis filter. Gain compensation is composed of the Equalizer (EQ0) and the Gain (0dB/+12dB/+24dB). E0A15-0 bits, E0B13-0 bits and E0C15-0 bits set the coefficient of EQ0. GN1-0 bits...
  • Page 47 [AK4951A] (5) 4-band Equalizer & 1-band Equalizer after ALC This block can be used as equalizer or Notch Filter. 4-band equalizers (EQ2~EQ5) are switched ON/OFF independently by EQ2, EQ3, EQ4 and EQ5 bits. EQ1 bit controls ON/OFF switching of the equalizer after ALC (EQ1).
  • Page 48 [AK4951A] Note 37. [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 2 X should be rounded to integer, and then should be translated to binary code (2’s complement).
  • Page 49 [AK4951A] Common Gain Sequence Examples <When noise is generated> EQCn bit = “0” EQCn bit = “1” EQn Gain (EQnG5-0 bits) (assuming the noise continues) (1) Set EQCn bit: “1” → “0” (Path Setting). The gain changes immediately by this setting.

  • Page 50: Alc Operation

    [AK4951A] ■ ALC Operation The ALC (Automatic Level Control) is operated by ALC block. When ADCPF bit is “1”, the ALC circuit operates for recording path, and the ALC circuit operates for playback path when ADCPF bit is “0”. ALC bit controls ON/OFF of ALC operation.
  • Page 51 [AK4951A] 1. ALC Limiter Operation During ALC limiter operation, when either L or R channel output level exceeds the ALC limiter detection level (Table 35), the VOL value (same value for both L and R) is attenuated automatically by the amount...
  • Page 52 [AK4951A] 2. ALC Recovery Operation ALC recovery operation wait for the WTM1-0 bits (Table 37) to be set after completing ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 35) during the wait time, ALC recovery operation is executed. The VOL value is automatically incremented by the...
  • Page 53 [AK4951A] Table 39. Reference Level of ALC Recovery Operation REF7-0 bits GAIN (dB) Step +36.0 +35.625 +35.25 +30.0 (default) 0.375dB +0.375 –0.375 –52.125 –52.5 04H~00H MUTE Table 40. Fast Recovery Speed Setting (FRN bit = “0”) RFST1-0 bits Fast Recovery Gain Step [dB] 0.0032...
  • Page 54 [AK4951A] 4. Example of ALC Setting Table 43 Table 44 show the examples of the ALC setting for recording and playback path. Table 43. Example of the ALC Setting (Recording) fs=8kHz fs=48kHz Register Comment Name Data Operation Data Operation 4.1dBFS 4.1dBFS...
  • Page 55 The following registers must not be changed during ALC operation. These bits must be changed after ALC operation is stopped by ALC bit = “0”. ALC output is “0” data until the AK4951A becomes manual mode after writing “0” to ALC bit.

  • Page 56: Input Digital Volume (Manual Mode)

    [AK4951A] ■ Input Digital Volume (Manual Mode) The input digital volume becomes manual mode when ALC bit is set to “0” while ADCPF bit is “1”. This mode is used in the cases shown below. 1. After exiting reset state, when setting up the registers for ALC operation (LMTH and etc.) 2.

  • Page 57: Sidetone Digital Volume

    ■ Output Digital Volume The AK4951A has a digital output volume (205 levels, 0.5dB step, Mute). The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –89.5dB or MUTE. DVL7-0 bits control both Lch and Rch volumes together when DVOLC bit = “1”...

  • Page 58: Soft Mute

    [AK4951A] Table 50. Output Digital Volume Setting DVL7-0 bits Gain Step DVR7-0 bits +12.0dB +11.5dB +11.0dB 0.5dB (default) 89.0dB 89.5dB Mute ( ) CCH~FFH Table 51. Transition Time Setting of Output Digital Volume Transition Time between DVTM bit DVL/R7-0 bits = 00H and CCH...

  • Page 59: Beep Input

    SPKG1-0 bits setting. When the BEEP signal is output to the stereo headphone amplifier, AK4951A operates without the system clock. In order to operate the charge pump circuit, it is necessary to power up the internal oscillator (PMOSC bit = “1”).
  • Page 60 [AK4951A] To MIC-Amp BPLVL3-0 bits “0” RIN3/BEEP pin BEEPH bit “1” To Headphone-Amp PMBP bit BEEPS bit BEEP-Amp To Speaker-Amp or Lineout-Amp Figure 41. Block Diagram of BEEP pin 016001936-E-00 2016/03 - 60 - Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 61: Charge Pump Circuit

    [AK4951A] ■ Charge Pump Circuit The internal charge pump circuit generates negative voltage (VEE) from AVDD voltage. The VEE voltage is used for the headphone amplifier. The charge pump circuit starts operation when PMHPL or PMHPR bit = “1”. PMVCM bit must be set “1” to power up the charge pump circuit. When the BEEP signal is output to the stereo headphone amplifier without the system clock, the charge pump circuit can be operated using the internal oscillator by setting PMOSC bit = “1”.

  • Page 62: Speaker Output (Spp/Spn Pins, Losel Bit = "0")

    (Note 42). Because the SPP and SPN pins rise up in power-save mode, pop noise can be reduced. When the AK4951A is powered-down (PMSL bit = “0”), pop noise can also be reduced by first entering power-save-mode. Note 42. When the SVDD more than 4.6V is supplied, the voltage cannot rise up to SVDD/2.

  • Page 63: Thermal Shutdown Function

    [AK4951A] LOSEL bit Don't care "L" PMSL bit SLPSN bit >1ms >0ms SPP pin Hi-Z Hi-Z SVDD/2 SVDD/2 (AVDD/2) (AVDD/2) SPN pin Figure 43. Power-up/Power-down Timing for Speaker-Amp ■ Thermal Shutdown Function When the internal temperature of the device rises up irregularly (e.g. Output pins of speaker-amp or headphone-amp are shortened), the speaker-amp, the headphone-amp and charge-pump circuit are automatically powered down and then THDET bit becomes “1”...

  • Page 64: Stereo Line Output (Lout/Rout Pin, Losel Bit = "1")

    [AK4951A] ■ Stereo Line Output (LOUT/ROUT pin, LOSEL bit = “1”) When LOSEL bit is set to “1”, L and R channel signals of DAC are output in single-ended format via LOUT and ROUT pins. The stereo line output is valid at SVDD = 2.8~3.5V. The same voltage as AVDD must be supplied to the stereo lineout.
  • Page 65 [AK4951A] LOUT 1F 220 ROUT External Input 22k Note 43. If the value of 22k resistance at pop noise reduction circuit is increased, the power-up time of stereo line output is increased but the pop noise level is not decreased. Do not use a resistor less than 22k...

  • Page 66: Regulator Block

    ■ Regulator Block The AK4951A integrates a regulator. The 3.3V (typ) power supply voltage from the AVDD pin is converted to 2.3V (typ) by the regulator and supplied to the analog blocks (MIC-Amp, ADC, DAC, BEEP). The regulator is powered up by PMVCM bit = “1”, and powered down by PMVCM = “0”. Connect a 2.2µF (±...

  • Page 67: Serial Control Interface

    56). A R/W bit value of “1” indicates that the read operation is to be executed, and “0” indicates (Figure that the write operation is to be executed. The second byte consists of the control register address of the AK4951A. The format is MSB first, and those most significant 1bit is fixed to zero (Figure 51).
  • Page 68 [AK4951A] R/W="0" Slave Data(n) Data(n+1) Data(n+x) Address Address(n) Figure 49. Data Transfer Sequence at I C Bus Mode Figure 50. The First Byte Figure 51. The Second Byte Figure 52. The Third Byte 016001936-E-00 2016/03 - 68 - Arrow.com. Arrow.com.
  • Page 69 [AK4951A] 2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4951A. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
  • Page 70 [AK4951A] start condition stop condition Figure 55. Start Condition and Stop Condition DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER clock pulse for acknowledgement START CONDITION Figure 56. Acknowledge (I C Bus) data line change stable;...

  • Page 71: Register Map

    [AK4951A] ■ Register Map Addr Register Name Power Management 1 PMPFIL PMVCM PMBP PMDAC PMADR PMADL Power Management 2 PMOSC PMHPR PMHPL PMPLL PMSL LOSEL Signal Select 1 SLPSN MGAIN3 DACS MPSEL PMMP MGAIN2 MGAIN1 MGAIN0 Signal Select 2 SPKG1...
  • Page 72 [AK4951A] Addr Register Name Digital Filter Select 3 Device Information REV3 REV2 REV1 REV0 DVN3 DVN2 DVN1 DVN0 E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1 E1A0 E1 Co-efficient 1 E1A15 E1A14 E1A13 E1A12 E1A11 E1A10 E1A9 E1A8...

  • Page 73: Register Definitions

    PMPFIL: Programmable Filter Block Power Management 0: Power down (default) 1: Power up The AK4951A can be powered down by writing “0” to the address “00H” and PMPLL, PMMP, PMHPL, PMHPR, PMSL, PMDML, PMDMR and PMOSC bits. In this case, register values are maintained.
  • Page 74 [AK4951A] Addr Register Name Power Management 2 PMOSC PMHPR PMHPL PMPLL PMSL LOSEL Default LOSEL: Stereo Line Output Select 0: Speaker Output (SPP/SPN pins) (default) 1: Stereo Line Output (LOUT/ROUT pins) PMSL: Speaker Amplifier or Stereo Line Output Power Management...
  • Page 75 [AK4951A] Addr Register Name Signal Select 1 SLPSN MGAIN3 DACS MPSEL PMMP MGAIN2 MGAIN1 MGAIN0 Default MGAIN3-0: Microphone Amplifier Gain Control (Table Default: “0110” (+18dB) PMMP: MPWR pin Power Management 0: Power down: Hi-Z (default) 1: Power up MPSEL: MPWR Output Select...
  • Page 76 [AK4951A] Addr Register Name Signal Select 2 SPKG1 SPKG0 VODETN MICL INL1 INL0 INR1 INR0 Default INR1-0: ADC Rch Input Source Select (Table Default: “00” (RIN1 pin) INL1-0: ADC Lch Input Source Select (Table Default: “00” (LIN1 pin) MICL: MPWR pin Output Voltage Select 0: typ 2.4V (default)
  • Page 77 [AK4951A] Addr Register Name Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO CKOFF DIF1 DIF0 Default DIF1-0: Audio Interface Format (Table Default: “10” (MSB justified) CKOFF: LRCK, BICK and SDTO Output Setting in Master Mode 0: LRCK, BICK and SDTO Output (default) 1: LRCK, BICK and SDTO Stop ( “L”...
  • Page 78 [AK4951A] Addr Register Name Mode Control 3 TSDSEL THDET SMUTE DVOLC IVOLC Default IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume levels, while register values of IVL7-0 bits are not written to IVR7-0 bits.
  • Page 79 [AK4951A] Addr Register Name Digital MIC PMDMR PMDML DCLKE DCLKP DMIC Default DMIC: Digital Microphone Connection Select 0: Analog Microphone (default) 1: Digital Microphone DCLKP: Data Latching Edge Select 0: Lch data is latched on the DMCLK rising edge (“”). (default) 1: Lch data is latched on the DMCLK falling edge (“”).
  • Page 80 [AK4951A] Addr Register Name ALC Timer Select IVTM EQFC1 EQFC0 WTM1 WTM0 RFST1 RFST0 Default RFST1-0: ALC First Recovery Speed (Table Default: “00” (0.0032dB) WTM1-0: ALC Recovery Waiting Period (Table Default: “00” (128/fs) EQFC1-0: ALCEQ Frequency Setting (Table Default: “10” (Extreme value=150Hz, Zero point=100Hz @ fs = 48kHz)
  • Page 81 [AK4951A] Addr Register Name Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 Default IVL7-0, IVR7-0: Digital Input Volume; 0.375dB step, 242 Level (Table Default: “E1H” (+30.0dB)
  • Page 82 [AK4951A] Addr Register Name Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0 Rch Digital Volume Control DVR7 DVR6 DVR5 DVR4 DVR3 DVR2 DVR1 DVR0 Default DVL7-0, DVR7-0: Digital Output Volume (Table Default: “18H” (0dB) Addr Register Name...
  • Page 83 [AK4951A] Addr Register Name Auto HPF Control AHPF SENC2 SENC1 SENC0 STG1 STG0 Default STG1-0: Automatic Wind Noise Reduction Filter Maximum Attenuation Level (Table Default: “00” (Low) SENC2-0: Wind Noise Detection Sensitivity (Table Default: “011” (2.0) AHPF: Automatic Wind Noise Reduction Filter Control...
  • Page 84 [AK4951A] Addr Register Name Digital Filter Select 2 FIL3 Default HPF: HPF2 Coefficient Setting Enable 0: OFF (default) 1: ON When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPF bit is “0”, the audio data passes the HPF2 block by is 0dB gain.
  • Page 85 [AK4951A] Addr Register Name HPF2 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0 HPF2 Co-efficient 1 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8 HPF2 Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0 HPF2 Co-efficient 3 F1B13 F1B12...
  • Page 86 REV3 REV2 REV1 REV0 DVN3 DVN2 DVN1 DVN0 Default DVN3-0: Device No. ID (Read operation only.) 0001: AK4951 REV3-0: Device Revision ID (Read operation only.) 1101: AK4951A 016001936-E-00 2016/03 - 86 - Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 87 [AK4951A] Addr Register Name E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1 E1A0 E1 Co-efficient 1 E1A15 E1A14 E1A13 E1A12 E1A11 E1A10 E1A9 E1A8 E1 Co-efficient 2 E1B7 E1B6 E1B5 E1B4 E1B3 E1B2 E1B1 E1B0 E1 Co-efficient 3...

  • Page 88: Recommended External Circuits

    - All digital input pins must not be allowed to float. - When the AK4951A is used in master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, a pull-up or pull-down resistor around 100k must be connected to LRCK and BICK pins of the AK4951A.
  • Page 89 1) Power-up - The PDN pin should be held “L” when power supplies are turning on. The AK4951A can be reset by keeping the PDN pin “L” for 200ns or longer after all power supplies are applied and settled.
  • Page 90 [AK4951A] 6. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit data).

  • Page 91: Control Sequence

    (4) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source, and PLL lock time is 5ms (max) (5) The AK4951A starts to output the LRCK and BICK clocks after the PLL became stable. Then normal operation starts.
  • Page 92 <Sequence> (1) After Power Up: PDN pin “L” → “H” “L” time of 200ns or more is needed to reset the AK4951A. (2) After Dummy Command (Addr:00H, Data:00H) input, DIF1-0, PLL3-0, and FS3-0 bits must be set during this period.
  • Page 93 <Sequence> (1) After Power Up: PDN pin “L” → “H” “L” time of 200ns or more is needed to reset the AK4951A. (2) After Dummy Command (Addr:00H, Data:00H) input, DIF1-0, CM1-0 and FS3-0 bits must be set during this period.

  • Page 94: Microphone Input Recording (Stereo)

    Table (1) Set up a sampling frequency (FS3-0 bits). When the AK4951A is in PLL mode, Microphone, ADC and Programmable Filter of (12) must be powered-up in consideration of PLL lock time after a sampling frequency is changed.

  • Page 95: Digital Microphone Input (Stereo)

    Table (1) Set up a sampling frequency (FS3-0 bits). When the AK4951A is PLL mode, Digital Microphone of (11) and Programmable Filter of (10) must be powered-up in consideration of PLL lock time after a sampling frequency is changed.

  • Page 96: Headphone Amplifier Output

    At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up the sampling frequency (FS3-0 bits). When the AK4951A is PLL mode, the Headphone Amplifier and DAC of (4) must be powered-up in consideration of PLL lock time after the sampling frequency is changed.

  • Page 97: Beep Signal Output From Headphone Amplifier

    Figure 66. “BEEP-Amp → Headphone-Amp” Output Sequence <Sequence> Clock input is not necessary when the AK4951A is operating only on the path of “BEEP-Amp → Headphone-Amp”. (1) Power up VCOM and BEEP Amplifier: PMVCM = PMBP bit = “0” → “1”...
  • Page 98 [AK4951A] 2. Power up DAC → Headphone Amplifier Example: default (1) Addr:00H, D5 bit = “1” PMBP bit (Addr:00H, D5) (2) Addr:12H, D4 bit = “1” BEEPH bit (Addr:12H, D4) PTS1-0 PTS1-0 BEEP Signal Output bits bits (3) Addr:12H, D4 bit = “0”...

  • Page 99: Speaker Amplifier Output

    At first, clocks must be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4951A is in PLL mode, DAC, Programmable Filter and Speaker-Amp of (11) must be powered-up in consideration of PLL lock time after a sampling frequency is changed.

  • Page 100: Beep Signal Output From Speaker Amplifier

    (7) Addr:03H, Data:00H Figure 69. “BEEP-Amp → Speaker-Amp” Output Sequence <Sequence> Clock input is not necessary when the AK4951A is operating only on the path of “BEEP-Amp” → “SPK-Amp”. (1) Enter Speaker-Amp Output Mode: LOSEL bit = “0” (2) Power up VCOM, MIN-Amp and Speaker: PMVCM = PMBP = PMSL bits = “0” → “1”...

  • Page 101: Stop Of Clock

    [AK4951A] ■ Stop of Clock When ADC, DAC or Programmable Filter is powered-up, the clocks must be supplied. PLL Master Mode Example: Audio I/F Format: I2S Compatible (ADC & DAC) PMPLL bit BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 12MHz...

  • Page 102: Power Down

    [AK4951A] EXT Master Mode Example External MCKI Input Audio I/F Format: I2S Compatible (ADC & DAC) Input MCKI frequency: 256fs BICK Output "H" or "L" (1) Stop the external MCKI LRCK Output "H" or "L" Figure 73. Clock Stopping Sequence (4) <Sequence>...

  • Page 103: Package

    [AK4951A] 12. Package ■ Outline Dimensions 32-pin QFN (Unit: mm) 0.75 ± 0.05 2.8 ± 0.1 Exposed 0~0.05 4.0 ± 0.1 C0.35 0.40 0.20 ± 0.05 0.10 M C A B 0.08 C Note. The exposed pad on the bottom surface of the package must be connected to the ground.

  • Page 104: Ordering Guide

    [AK4951A] 13. Ordering Guide 40  +85C AK4951AEN 32-pin QFN (0.4mm pitch) AKD4951AEN Evaluation board for AK4951AEN 14. Revision History Date (Y/M/D) Revision Reason Page Contents 15/03/18 First Edition 016001936-E-00 2016/03 - 104 - Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 105: Important Notice

    AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications.

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