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AKM AsahiKASEI AK4675 Manual

Stereo codec with mic/rcv/hp/spk-amp
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The AK4675 is a stereo CODEC with a built-in Microphone-Amplifier, Receiver-Amplifier, cap-less
Headphone-Amplifier and stereo audio class-D Speaker-Amplifier. The AK4675 features dual PCM I/F in
addition to audio I/F that allows easy interfacing in mobile phone designs with Bluetooth I/F. The
Speaker-Amplifier includes ALC (Automatic Level Control) circuit what is able to stabilize each output
sound levels. The AK4675 is available in an 83pin BGA, utilizing less board space than competitive
offerings.
1. Recording Function (Stereo CODEC)
• 4 Stereo Input Selector x 2ch
• 4 Stereo Inputs (Single-ended) or 2 Stereo Input (Full-differential)
• MIC Amplifier: +30dB ∼ −12dB, 3dB step
• Digital ALC (Automatic Level Control): +36dB ∼ −54dB, 0.375dB Step, Mute
• Wind-noise Reduction Filter
• Stereo Separation Emphasis
• 5-band Programmable Notch Filter
• Audio Interface Format: 16bit MSB justified, I
2. Playback Function (Stereo CODEC)
• Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control): +36dB ∼ −54dB, 0.375dB Step, Mute
• Stereo Separation Emphasis
• 5-band EQ
• Stereo Line Output
• Mono Receiver-Amp
• Stereo Cap-less Headphone Amplifier
• Class-D Speaker Amplifier
• Thermal Shutdown / Short protection circuit
• Analog Mixing: 4 Stereo Input
• Audio Interface Format: 16bit MSB justified, 16bit LSB justified, 16-24bit I
3. Dual PCM I/F for Baseband & Bluetooth Interface
MS0963-E-00
Stereo CODEC with MIC/RCV/HP/SPK-AMP
GENERAL DESCRIPTION
- BTL Output
- Output Power: 30mW@32Ω (AVDD=3.3V)
- Mono / Stereo Mode
- Output Power: 64mW x 2ch @ 16Ω, SVDDA=3.3V, THD+N = –40dB
- THD+N: -58dB @ 16Ω, Po=30mW, SVDDA=3.3V
- Output Noise Level: 24μVrms
- Outputs Volume: +12dB to –50dB, 2dB Step
- Pop Noise Free at Power-ON/OFF and Mute
- BTL output
- Output Power: 1.6W @ 8Ω, SVDDA=5.0V
0.8W @ 8Ω, SVDDA=3.6V
- THD+N: –65dB @8Ω, Po=0.25W, SVDDA=3.6V
- Output Noise Level: 71μVrms
- ALC (Automatic Level Control) Circuit
- Pop Noise Free at Power-ON/OFF and Mute
- External filter-less
- Short Protection circuit
FEATURES
Mode
- 1 -
AK4675
2
S, DSP Mode
[AK4675]
2
S, DSP
2008/05

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Summary of Contents for AKM AsahiKASEI AK4675

  • Page 1 [AK4675] AK4675 Stereo CODEC with MIC/RCV/HP/SPK-AMP GENERAL DESCRIPTION The AK4675 is a stereo CODEC with a built-in Microphone-Amplifier, Receiver-Amplifier, cap-less Headphone-Amplifier and stereo audio class-D Speaker-Amplifier. The AK4675 features dual PCM I/F in addition to audio I/F that allows easy interfacing in mobile phone designs with Bluetooth I/F. The Speaker-Amplifier includes ALC (Automatic Level Control) circuit what is able to stabilize each output sound levels.

  • Page 2: Pll Mode

    [AK4675] • Sample Rate Converter (Up sample: up to x6: Down sample: down to x1/6) • Sample Rate: 8kHz • Digital Volume • Audio Interface Format: - 16bit Linear, 8bit A-law, 8bit μ-law - Short/Long Frame, I S, MSB justified 4.
  • Page 3 [AK4675] Block Diagram (CODEC Block) AVDD VSS1 VCOM SAIN2 SAVDD VSS3 DVDD SAIN1 SAIN3 VSS4 TEST GPO1 GPO2 PMSAD MPWR PMMP TEST5 MPWR MIC Power Control Supply Register MIC-Amp TEST4 PMMICL LIN1/IN1+ PMADL or PMADR TEST6 Internal RIN1/IN1− LIN2/IN2 PMMICR External PFSEL=0 RIN2/IN2...
  • Page 4 [AK4675] Block Diagram (HP/SPK-Amp Block) TEST3 TEST2 AVDDA VSS1A SVDDA PMSP SPIN ALCA VSS2A PMMHL PMHPL PMV1 Mixing LIN1A Selector Mixing RIN1A Selector PMHPR PMMHR PMVCMA VCOMA VCOMA Int Osc or Ext Clock MCKIA PMOSC TVDDA PMCP Charge Serial I/F Pump VBATIN VBATO PVDDA VSS3A PVEE...
  • Page 5 [AK4675] Ordering Guide −30 ∼ +85°C AK4675EG 83pin BGA (0.5mm pitch) AKD4675 Evaluation board for AK4675 Pin Layout AK4675 Top View TEST VCOM VCOC PVDDA VSS3A SDTIA GPO2 ROUT1 AVDD VBATO VCOCBT PVEE SDTOA SYNCA PDNA BICKA /RCN ROUT3 RIN4 VSS1 VCOMA PVDD...
  • Page 6 [AK4675] PIN/FUNCTION Pin Name Function MIC Detection Pin (Internal pull down by typ. 500kΩ) MPWR MIC Power Supply Pin SAIN3 10bit SAR ADC Analog Input 3 Pin SAIN2 10bit SAR ADC Analog Input 2 Pin SAIN1 10bit SAR ADC Analog Input 1 Pin SAVDD 10bit SAR ADC Power Supply Pin 2.2V ~ 3.6V...
  • Page 7 [AK4675] Pin Name Function SDTIA Serial Data Input A Pin BICKA Serial Data Clock A Pin SYNCA Sync Signal A Pin SDTOA Serial Data Output A Pin TVDD2 Digital I/O Power Supply 2 Pin for CODEC 1.6V ~ 3.6V VSS2 Ground 2 Pin for CODEC PVDD PLLBT Power Supply Pin...
  • Page 8 [AK4675] Pin Name Function Test 2 Pin TEST2 This pin must be open. No Connect Pin No internal bonding. This pin must be opened or connected to the ground. AVDDA HP/SPK-Amp Analog Power Supply Pin 2.6V ~ 3.6V VSS1A HP/SPK-Amp Ground 1 Pin HP/SPK-Amp Digital Interface Power Supply Pin 1.6V ~ 3.6V TVDDA...
  • Page 9 [AK4675] Handling of Unused Pins The unused I/O pins must be processed appropriately as below. Classification Pin Name Setting MPWR, MDT, VCOC, ROUT3/LON, LOUT3/LOP, ROUT2S, LOUT2S, ROUT1/RCN, LOUT1/RCP, RIN4/IN4−, LIN4/IN4+, RIN3/IN3−, LIN3/IN3+, Analog These pins msut be open. RIN2/IN2−, LIN2/IN2+, RIN1/IN1−, LIN1/IN1+, VCOCBT, SAIN1, SAIN2, SAIN3, HPL, HPR, SPIN, SPP, SPN, LIN1A, RIN1A, VBATIN, VBATO, TEST2 MCKO, SDTOA, SDTOB, GPO1, GPO2, BICKA,...

  • Page 10: Absolute Maximum Ratings

    [AK4675] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V; Note Note Parameter Symbol Units −0.3 Power Supplies: CODEC Analog AVDD −0.3 (Note PLLBT PVDD −0.3 10bit SAR ADC SAVDD −0.3 CODEC Digital DVDD −0.3 CODEC Digital I/O 2 TVDD2 −0.3 CODEC Digital I/O 3 TVDD3 −0.3 HP/SPK-Amp Analog...

  • Page 11: Recommended Operating Conditions

    [AK4675] RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V; Note Parameter Symbol Units Power Supplies CODEC Analog AVDD (Note 16) PLLBT PVDD 10bit SAR ADC SAVDD CODEC Digital DVDD CODEC Digital I/O 2 TVDD2 CODEC Digital I/O 3 TVDD3 HP/SPK-Amp Analog AVDDA HP/SPK-Amp Digital I/F TVDDA Speaker-Amp &...
  • Page 12 [AK4675] ANALOG CHARACTERISTICS (CODEC) (Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=AVDDA=PVDDA=TVDDA=3.3V, SVDDA=3.6V; VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V; Signal Frequency=1kHz; 16bit Data; fs=44.1kHz, BICK=64fs, LP bit = “0”; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Units Parameter MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins; PMAINL1/R1/L2/R2/L3/R3/L4/R4 bits = “0” Input Resistance MGNL/R0 bit = “0” kΩ...
  • Page 13 [AK4675] Units Parameter Stereo DAC Characteristics: Resolution Bits Stereo Line Output Characteristics: Stereo DAC → LOUT1/ROUT1/LOUT3/ROUT3 pins, ALC=OFF, IVOL=0dB, OVOL=0dB, L1VL=L3VL=0dB, RCV bit = “0”, R =10kΩ; unless otherwise specified. Output Voltage (Note 1.78 1.98 2.18 S/(N+D) (0dBFS) S/N (A-weighted) Interchannel Isolation Interchannel Gain Mismatch Load Resistance...
  • Page 14 [AK4675] Units Parameter Mono Line Output Characteristics: Stereo DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, OVOL=0dB, L3VL=0dB, LODIF bit = “1”, R =10kΩ for each pin (Full-differential) Output Voltage (Note 3.52 3.96 4.36 S/(N+D) (0dBFS) S/N (A-weighted) Load Resistance (LOP/LON pins, respectively) kΩ...
  • Page 15 [AK4675] ANALOG CHARACTERISTICS (HP/SPK-Amp) (Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=AVDDA=PVDDA=TVDDA=3.3V, SVDDA=3.6V; VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz ∼ 20kHz; Headphone-Amp: R =16Ω; Speaker-Amp: R =8Ω + 10μH; Charge Pump Circuit External Capacitance: C1=C2= 2.2μF (Figure 3); unless otherwise specified) Parameter Units LIN1A, RIN1A pins Input Resistance kΩ...
  • Page 16 [AK4675] Note 31. PSR is applied to AVDDA and PVDDA with 100mVpp. This is the value of convoluting sinusoidal voltage of 100mVpp. Note 32. PSR is applied to SVDDA with 0.89Vpp. This is the value of convoluting sinusoidal voltage of 100mVpp. Note 33.
  • Page 17 [AK4675] ANALOG CHARACTERISTICS (Power Supply Current) (Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=AVDDA=PVDDA=TVDDA=3.3V, SVDDA=3.6V; VSS1=VSS2=VSS3=VSS4=VSS1A=VSS2A=VSS3A=0V; Signal Frequency=1kHz; 16bit Data; fs=44.1kHz, BICK=64fs, LP bit = “0”; Measurement frequency=20Hz ∼ 20kHz; Headphone-Amp: R =16Ω; Speaker-Amp: R =8Ω + 10μH; Charge Pump Circuit External Capacitance: C1=C2=2.2μF (Figure 3); unless otherwise specified) Parameter Units Power Supplies:...
  • Page 18 [AK4675] SRC CHARACTERISTICS (Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 3.4kHz; unless otherwise specified) Parameter Symbol Units SRC Characteristics (Down Sampling: SRC-A): SDTI å SRC-A å SDTOA/SDTOB Resolution Bits Input Sample Rate (Note FSI (fs) Output Sample Rate (Note FSO (fs2) THD+N (Input = 1kHz, −1dBFS,...
  • Page 19 [AK4675] ANALOG CHARACTERISTICS (10bit SAR ADC) (Ta=25°C; AVDD=PVDD=SAVDD=DVDD=TVDD2=TVDD3=3.3V; VSS1=VSS2=VSS3=VSS4=0V; unless otherwise specified) Parameter Units 10bit SAR ADC Characteristics Resolution Bits No Missing Codes Bits ±2 Integral Linearity Error ±1 Analog Input Voltage Range SAVDD ±3 Offset Error ±2 Gain Error ±1 Accuracy (Note...
  • Page 20 [AK4675] FILTER CHARACTERISTICS (CODEC) (Ta=25°C; AVDD=PVDD=SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2=TVDD3=1.6 ∼ 3.6V; fs=44.1kHz; Programmable Filter=OFF) Parameter Symbol Units ADC Digital Filter (Decimation LPF): ±0.16dB Passband (Note 17.3 −0.66dB 19.4 −1.1dB 19.9 −6.9dB 22.1 Stopband 25.9 ±0.1 Passband Ripple Stopband Attenuation Group Delay (Note 1/fs ΔGD...
  • Page 21 [AK4675] FILTER CHARACTERISTICS (SRC) (Ta=25°C; AVDD=PVDD=SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2=TVDD3=1.6 ∼ 3.6V; fs2=8kHz; Programmable Filter=OFF) Parameter Symbol Units Down Sampling (SRC-A): fs=8kHz ±0.15dB Passband Stopband ±0.15 Passband Ripple Stopband Attenuation Group Delay (Note Down Sampling (SRC-A): fs=11.025kHz ±0.15dB Passband Stopband ±0.15 Passband Ripple Stopband Attenuation Group Delay...
  • Page 22 [AK4675] Parameter Symbol Units Down Sampling (SRC-A): fs=32kHz ±0.1dB Passband Stopband ±0.1 Passband Ripple Stopband Attenuation Group Delay (Note Down Sampling (SRC-A): fs=44.1kHz ±0.1dB Passband Stopband ±0.1 Passband Ripple Stopband Attenuation Group Delay (Note Down Sampling (SRC-A): fs=48kHz ±0.1dB Passband Stopband ±0.1 Passband Ripple...
  • Page 23 [AK4675] Parameter Symbol Units Up Sampling (SRC-B): fs=8kHz ±0.1dB Passband Stopband ±0.1 Passband Ripple Stopband Attenuation Group Delay (Note Up Sampling (SRC-B): fs=11.025kHz ±0.1dB Passband Stopband ±0.1 Passband Ripple Stopband Attenuation Group Delay (Note Up Sampling (SRC-B): fs=12kHz ±0.1dB Passband Stopband ±0.1 Passband Ripple...
  • Page 24 [AK4675] Parameter Symbol Units Up Sampling (SRC-B): fs=32kHz ±0.1dB Passband Stopband ±0.1 Passband Ripple Stopband Attenuation Group Delay (Note Up Sampling (SRC-B): fs=44.1kHz ±0.1dB Passband Stopband ±0.1 Passband Ripple Stopband Attenuation Group Delay (Note Up Sampling (SRC-B): fs=48kHz ±0.1dB Passband Stopband ±0.1 Passband Ripple...
  • Page 25 [AK4675] DC CHARACTERISTICS (CODEC, SRC) (Ta=25°C; AVDD=PVDD=SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2=TVDD3=1.6 ∼ 3.6V) Parameter Symbol Units High-Level Input Voltage 1 2.2V≤DVDD≤3.6V VIH1 70%DVDD (Note 1.6V≤DVDD<2.2V VIH1 80%DVDD Low-Level Input Voltage 1 2.2V≤DVDD≤3.6V VIL1 30%DVDD (Note 1.6V≤DVDD<2.2V VIL1 20%DVDD High-Level Input Voltage 2 2.2V≤TVDD2≤3.6V VIH2 70%TVDD2...
  • Page 26 [AK4675] SWITCHING CHARACTERISTICS (CODEC, SRC) (Ta=25°C; AVDD=PVDD=SAVDD=2.2 ∼ 3.6V; DVDD=TVDD2=TVDD3=1.6 ∼ 3.6V; C =20pF (except SDA pin) or 400pF (SDA pin); unless otherwise specified) Parameter Symbol Units PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 Pulse Width Low...
  • Page 27 [AK4675] Parameter Symbol Units PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency 1/fs − tBCK DSP Mode: Pulse Width High tLRCKH tBCK−60 Except DSP Mode: Duty Cycle Duty BICK Input Timing Period tBCK 1/(64fs) 1/(32fs) Pulse Width Low tBCKL Pulse Width High...
  • Page 28 [AK4675] Parameter Symbol Units Audio Interface Timing (DSP Mode) Master Mode 0.5 x tBCK − 40 tDBF 0.5 x tBCK 0.5 x tBCK + 40 LRCK “↑” to BICK “↑” (Note 0.5 x tBCK − 40 LRCK “↑” to BICK “↓” (Note tDBF 0.5 x tBCK...
  • Page 29 [AK4675] Parameter Symbol Units PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins; Slave Mode): SYNCA Timing Frequency Serial Interface Timing at Short/long Frame Sync BICKA Frequency fBCK2 2048 BICKA Period tBCK2 BICKA Pulse Width Low tBCKL2 Pulse Width High tBCKH2 tSYB2 SYNCA Edge to BICKA “↑”...
  • Page 30 [AK4675] Parameter Symbol Units PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins; Master Mode): SYNCA Timing Frequency BICKA Timing Period (BCKO2 bit = “0”) tBCK2 1/(16fs2) (BCKO2 bit = “1”) tBCK2 1/(32fs2) Duty Cycle dBCK2 Serial Interface Timing at Short/long Frame Sync 0.5 x tBCK2 −...
  • Page 31 [AK4675] Parameter Symbol Units PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins; Slave Mode): SYNCB Timing Frequency Serial Interface Timing at Short/long Frame Sync BICKB Frequency fBCK3 2048 BICKB Period tBCK3 BICKB Pulse Width Low tBCKL3 Pulse Width High tBCKH3 tSYB3 SYNCB Edge to BICKB “↑”...
  • Page 32 [AK4675] Parameter Symbol Units PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins; Master Mode): SYNCB Timing Frequency BICKB Timing Period (BCKO2 bit = “0”) tBCK2 1/(16fs2) (BCKO2 bit = “1”) tBCK2 1/(32fs2) Duty Cycle dBCK2 Serial Interface Timing at Short/long Frame Sync 0.5 x tBCK2 −...
  • Page 33 [AK4675] Parameter Symbol Units Control Interface Timing (I C Bus mode): (Note SCL Clock Frequency (Note fSCL μs Bus Free Time Between Transmissions tBUF μs Start Condition Hold Time (prior to first clock pulse) tHD:STA μs Clock Low Time tLOW μs Clock High Time tHIGH...
  • Page 34 [AK4675] SWITCHING CHARACTERISTICS (HP/SPK-Amp) (Ta= 25°C; AVDDA=PVDDA=2.6 ∼ 3.6V; SVDDA=2.6 ∼ 5.5V; TVDDA=1.6 ∼ 3.6V) Parameter Symbol Units MCKIA Input Timing (OSCN bit = “1”) Frequency fCLK 2.048 3.072 Pulse Width Low fCLKL 0.4/fCLK Pulse Width High fCLKH 0.4/fCLK Power-down & Reset Timing PDNA Pulse Width (Note Note 76.
  • Page 35 [AK4675] Timing Diagram (CODEC, SRC) 1/fCLK VIH1 MCKI VIL1 tCLKH tCLKL 1/fs 50%DVDD LRCK tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK 50%DVDD BICK tBCKH tBCKL dBCK = tBCKH / tBCK x 100 tBCKL / tBCK x 100 1/fMCK MCKO...
  • Page 36 [AK4675] tLRCKH LRCK 50%DVDD tBCK tDBF dBCK BICK 50%DVDD (BCKP = "1") BICK 50%DVDD (BCKP = "0") tBSD SDTO 50%DVDD tSDS tSDH VIH1 SDTI VIL1 Figure 6. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS = “1”) 50%DVDD LRCK tBLR tBCKL BICK...
  • Page 37 [AK4675] 1/fs VIH1 LRCK VIL1 tLRCKH tBLR tBCK VIH1 BICK VIL1 (BCKP = "0") tBCKH tBCKL VIH1 BICK VIL1 (BCKP = "1") Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BICK pin, DSP mode, MSBS = “0”) 1/fs VIH1 LRCK...
  • Page 38 [AK4675] 1/fCLK VIH1 MCKI VIL1 tCLKH tCLKL 1/fs VIH1 LRCK VIL1 tLRCKH tLRCKL Duty = tLRCKH x fs x 100 = tLRCKL x fs x 100 tBCK VIH1 BICK VIL1 tBCKH tBCKL fMCK MCKO 50%DVDD tMCKL dMCK = tMCKL x fMCK x 100 Figure 10.
  • Page 39 [AK4675] tLRCKH VIH1 LRCK VIL1 tLRB VIH1 BICK VIL1 (BCKP = "1") VIH1 BICK VIL1 (BCKP = "0") tBSD SDTO 50%DVDD tSDH tSDS VIH1 SDTI VIL1 Figure 12. Audio Interface Timing (PLL Slave mode, DSP mode, MSBS = “1”) 1/fCLK VIH1 MCKI VIL1...
  • Page 40 [AK4675] VIH1 LRCK VIL1 tBLR tLRB VIH1 BICK VIL1 tLRD tBSD SDTO 50%DVDD tSDS tSDH VIH1 SDTI VIL1 Figure 14. Audio Interface Timing (PLL/EXT Slave mode, Except DSP mode) 1/fs2 VIH2 SYNCA VIL2 tSYH2 tSYL2 dSYC2 = tSYL2 x fs2 x 100 tBC K2 VIH 2 VIL2...
  • Page 41 [AK4675] VIH2 SYNCA VIL2 tSYB2 tBSY2 VIH2 BICKA VIL2 (BCKPA = “0”) VIH2 BICKA VIL2 (BCKPA = “1”) tSYD2 tBSD2 SDTOA 50%TVDD2 tSDS2 tSDH2 VIH2 SDTIA VIL2 Figure 16. PCM I/F A Timing at short and long frame sync (SYNCA, BICKA, SDTOA, SDTIA) VIH2 SYNCA VIL2...
  • Page 42 [AK4675] VIH2 SYNCA VIL2 tBSY2 tSYB2 VIH2 BICKA VIL2 tSYD2 tBSD2 SDTOA 50%TVDD2 tSDS2 tSDH2 VIH2 SDTIA VIL2 Figure 18. PCM I/F A Timing at MSB justified and I S (Slave mode) 1/fs2 50%TVDD2 SYNCA tSYH2 tSYL2 dSYC2 = tSYL2 x fs2 x 100 tBC K2 = 1/fBC K2 50% T VD D 2 BIC KA...
  • Page 43 [AK4675] SYNCA 50%TVDD2 tSYB2 BICKA 50%TVDD2 (BCKPA = “0”) BICKA 50%TVDD2 (BCKPA = “1”) tBSD2 SDTOA 50%TVDD2 tSDS2 tSDH2 VIH2 SDTIA VIL2 Figure 20. PCM I/F A Timing at short and long frame sync (Master mode; MSBSA = “0”) SYNCA 50%TVDD2 tSYB2 BICKA...
  • Page 44 [AK4675] 50%TVDD2 SYNCA tMBSY2 50%TVDD2 BICKA tSYD2 tBSD2 SDTOA 50%TVDD2 tSDS2 tSDH2 VIH2 SDTIA VIL2 Figure 22. PCM I/F A Timing at MSB justified and I S (Master mode) 1/fs2 VIH3 SYNCB VIL3 tSYH3 tSYL3 dSYC3 = tSYH3 x fs2 x 100 tSYL3 x fs2 x 100 tBC K3 = 1/fBC K3 VIH 3...
  • Page 45 [AK4675] VIH3 SYNCB VIL3 tSYB3 tBSY3 VIH3 BICKB VIL3 (BCKPB = “0”) VIH3 BICKB VIL3 (BCKPB = “1”) tSYD3 tBSD3 SDTOB 50%TVDD3 tSDS3 tSDH3 VIH3 SDTIB VIL3 Figure 24. PCM I/F B Timing at short and long frame sync (Slave mode; MSBSB = “0”) VIH3 SYNCB VIL3...
  • Page 46 [AK4675] VIH3 SYNCB VIL3 tBSY3 tSYB3 VIH3 BICKB VIL3 tSYD3 tBSD3 SDTOB 50%TVDD3 tSDS3 tSDH3 VIH3 SDTIB VIL3 Figure 26. PCM I/F B Timing at MSB justified and I S (Slave mode) 1/fs2 50%TVDD3 SYNCB tSYH3 tSYL3 dSYC3 = tSYL3 x fs2 x 100 tBC K3 = 1/fBC K3 50% T VD D 3 BIC KB...
  • Page 47 [AK4675] SYNCB 50%TVDD3 tSYB3 BICKB 50%TVDD3 (BCKPB = “0”) BICKB 50%TVDD3 (BCKPB = “1”) tBSD3 SDTOB 50%TVDD3 tSDS3 tSDH3 VIH3 SDTIB VIL3 Figure 28. PCM I/F B Timing at short and long frame sync (Master mode; MSBSB = “0”) SYNCB 50%TVDD3 tSYB3 BICKB...
  • Page 48 [AK4675] 50%TVDD3 SYNCB tMBSY3 50%TVDD3 BICKB tSYD3 tBSD3 SDTOB 50%TVDD3 tSDS3 tSDH3 VIH3 SDTIB VIL3 Figure 30. PCM I/F B Timing at MSB justified and I S (Master mode) VIH1 VIL1 tBUF tLOW tHIGH VIH1 VIL1 tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO Stop Start...
  • Page 49 [AK4675] PMADL bit PMADR bit tPDV SDTO 50%DVDD Figure 32. Power Down & Reset Timing 1 VIL1 Figure 33. Power Down & Reset Timing 2 PMSRA bit tPDV2 SDTOA 50%TVDD2 Figure 34. Power Down & Reset Timing 3 PMSRB bit tPDV3 SDTO 50%DVDD...
  • Page 50 [AK4675] Timing Diagram (HP/SPK-Amp) 1/fCLK VIH4 MCKIA VIL4 tCLKH tCLKL Figure 36. MCKIA Input Timing PDNA VIL4 Figure 37. Power-down & Reset Timing MS0963-E-00 2008/05 - 50 -...

  • Page 51: Operation Overview

    [AK4675] OPERATION OVERVIEW System Clock (Audio I/F) There are the following five clock modes to interface with external devices. (Table 1 Table Mode PMPLL bit M/S bit PLL3-0 bits Figure PLL Master Mode (Note Table 4 Figure 38 PLL Slave Mode 1 Table 4 Figure 39 (PLL Reference Clock: MCKI pin)
  • Page 52 [AK4675] PLL Mode (PMPLL bit = “1”) When PMPLL bit is “1”, an integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, when the AK4675 is supplied stable clock after PLL is powered-up (PMPLL bit = “0”...
  • Page 53 [AK4675] When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-2 bits (Table Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 8kHz ≤ fs ≤ 12kHz Don’t care Don’t care 12kHz <...
  • Page 54 [AK4675] PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to the MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit.
  • Page 55 [AK4675] PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the AK4675 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table a) PLL reference clock: MCKI pin The BICK and LRCK inputs should be synchronized with MCKO output.
  • Page 56 [AK4675] b) PLL reference clock: BICK or LRCK pin Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits. (Table AK4675 DSP or μP MCKO MCKI 32fs or 64fs BCLK BICK LRCK LRCK SDTI SDTO SDTO SDTI Figure 40. PLL Slave Mode 2 (PLL Reference Clock: BICK pin) AK4675 DSP or μP MCKO...
  • Page 57 [AK4675] EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4675 becomes EXT mode. Master clock is input from the MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (≥32fs).
  • Page 58 [AK4675] EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4675 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 384fs, 512fs, 768fs or 1024fs).

  • Page 59: System Reset

    [AK4675] System Reset The PDNA pin must keep “L” until all power supply pins are supplied, and must be set to “H”. After exiting reset (PDNA pin: “L” å “H”), all blocks of HP/SPK-Amp blocks (Input Volume, VCOMA, Oscillator, Mixer, Headphone-Amp, Speaker-Amp and charge pump circuit) switch to the power-down state.
  • Page 60 [AK4675] Audio Interface Format Four types of data formats are available and are selected by setting the DIF1-0 bits (Table 16). In all modes, the serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK are output from the AK4675 in master mode, but must be input to the AK4675 in slave mode.
  • Page 61 [AK4675] LRCK (Master) LRCK (Slave) BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 1/fs 15:MSB, 0:LSB Figure 44. Mode 0 Timing (BCKP = “0”, MSBS = “0”) LRCK (Master) LRCK (Slave) BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 1/fs 15:MSB, 0:LSB Figure 45. Mode 0 Timing (BCKP = “1”, MSBS = “0”) MS0963-E-00 2008/05 - 61 -...
  • Page 62 [AK4675] LRCK (Master) LRCK (Slave) BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 1/fs 15:MSB, 0:LSB Figure 46. Mode 0 Timing (BCKP = “0”, MSBS = “1”) LRCK (Master) LRCK (Slave) BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) SDTI(i) 1/fs 15:MSB, 0:LSB Figure 47. Mode 0 Timing (BCKP = “1”, MSBS = “1”) MS0963-E-00 2008/05 - 62 -...
  • Page 63 [AK4675] LRCK 11 12 13 14 15 0 1 2 3 11 12 13 14 15 BICK(32fs) 15 14 15 14 13 7 6 5 4 3 SDTO(o) 6 5 4 3 SDTI(i) 15 14 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 17 18...
  • Page 64 [AK4675] LRCK 11 12 13 14 15 0 1 2 3 11 12 13 14 15 BICK(32fs) SDTO(o) 15 14 6 5 4 3 15 14 7 6 5 4 3 2 1 0 15 14 7 6 5 4 3 2 1 0 15 14 7 6 5 4 3 2 1 0 SDTI(i)
  • Page 65 [AK4675] MIC/LINE Input Selector The AK4675 has input selector. When MDIF1, MDIF2, MDIF3 and MDIF4 bits are “0”, INL1-0 and INR1-0 bits select LIN1/LIN2/LIN3/LIN4 and RIN1/RIN2/RIN3/RIN4, respectively. When MDIF1, MDIF2, MDIF3 and MDIF4 bits are “1”, LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 pins become IN1+/−, IN2+/−, IN3+/− and IN4+/− pins, respectively.
  • Page 66 [AK4675] AK4675 INL1-0 bits LIN1/IN1+ pin ADC Lch RIN1/IN1− pin MIC-Amp Lch MDIF1 bit MDIF3 bit INR1-0 bits LIN2/IN2+ pin ADC Rch RIN2/IN2− pin MIC-Amp Rch MDIF2 bit MDIF4 bit LIN3/IN3+ pin RIN3/IN3− pin LIN4/IN4+ pin RIN4/IN4− pin Lineout Figure 51. Mic/Line Input Selector AK4675 MPWR pin MIC-Amp...
  • Page 67 [AK4675] MIC Gain Amplifier The AK4675 has a gain amplifier for microphone input. The gain of MIC-Amp Lch and Rch is independently selected by the MGNL3-0 and MGNR3-0 bits (Table 19). The typical input impedance is 42kΩ(typ)@MGNL/R0 bits = “0” or 30kΩ(typ)@MGNL/R0 bits = “1”.

  • Page 68: Mic Power

    [AK4675] MIC Power When PMMP bit = “1”, the MPWR pin supplies power for the microphone. This output voltage is typically 0.8 x AVDD and the load resistance is minimum 0.5kΩ. In case of using two sets of stereo mic, the load resistance is minimum 2kΩ for each channel.
  • Page 69 [AK4675] MIC Detection The AK4675 has a detect function of microphone inputs. The followings show the example of external microphone detection sequence: (1) PMMP bit should be set to “1” after CPU detects the jack insertion of microphone or headphone. (2) The MPWR pin drives external microphone.
  • Page 70 [AK4675] Digital Block Digital block is composed as Figure 56. Each block can be powered-down by power management bit (PMADL, PMADR, PMDAL, PMDAR, PMSRA, PMSRB and PMPCM bits). When blocks from HPF to MIX are powered-down, both MIX and SVOLA blocks should not be selected by SDOL/R bits and PFMXL/R bits. PMADL or PMADR HPFAD PFSEL...
  • Page 71 [AK4675] (1) ADC: Include the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”. (2) DAC: Include the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”. (3) HPF: High Pass Filter. Applicable to use as Wind-Noise Reduction Filter. (See “Digital Programmable Filter”.) (4) LPF: Low Pass Filter (See...
  • Page 72 [AK4675] Digital Programmable Filter (1) High Pass Filter (HPF) Normally, this HPF is used for a Wind-Noise Reduction Filter. This is composed with 2 steps of 1st order HPF. The coefficient of both HPF is the same and set by F1A13-0 bits and F1B13-0 bits. HPFAD bit controls ON/OFF of the 1st step HPF and HPF bit controls ON/OFF of the 2nd step HPF.
  • Page 73 [AK4675] (3) Stereo Separation Emphasis Filter (FIL3) FIL3 is used to emphasize the stereo separation of stereo mic recording data or playback data. F3A13-0 and F3B13-0 bits set the filter coefficient of FIL3. FIL3 becomes High Pass Filter (HPF) at F3AS bit = “0”, and Low Pass Filter (LPF) at F3AS bit = “1”.
  • Page 74 [AK4675] (4) Gain Compensation (EQ0) Gain Compensation is used to compensate the frequency response and the gain that is changed by Stereo Separation Emphasis Filter. Gain Compensation is composed with Equalizer (EQ0) and the Gain (0dB/+12dB/+24dB). E0A15-0, E0B13-0 and E0C15-0 bits set the coefficient of EQ0. GN1-0 bits set the gain (Table 23).
  • Page 75 [AK4675] (5) 5-band Notch This block can be used as Equalizer or Notch Filter. 5-band Equalizer (EQ1, EQ2, EQ3, EQ4 and EQ5) is ON/OFF independently by EQ1, EQ2, EQ3, EQ4 and EQ5 bits. When Equalizer is OFF, the audio data passes this block by 0dB gain.

  • Page 76: Alc Operation

    [AK4675] ALC Operation The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”. ALC circuit operates at playback path for Playback mode and operates at recording path for Recording mode as shown in Table 1. ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 24), the IVL...
  • Page 77 [AK4675] 2. ALC Recovery Operation ALC recovery operation waits for the WTM2-0 bits (Table 27) to be set after completing ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 24) during the wait time, ALC recovery operation is executed.
  • Page 78 [AK4675] REF7-0 bits GAIN (dB) Step +36.0 +35.625 +35.25 +30.0 (default) 0.375dB +0.375 −0.375 −53.625 −54.0 MUTE Table 29. Reference Level at ALC Recovery Operation RFST1 bit RFST0 bit Recovery Speed 4 times (default) 8 times 16times Table 30. Fast Recovery Speed Setting (N/A: Not available) MS0963-E-00 2008/05 - 78 -...
  • Page 79 [AK4675] 3. Example of ALC Operation Table 31 Table 32 show the examples of the ALC setting for mic recording and playback, respectively. fs=8kHz fs=44.1kHz Register Name Comment Data Operation Data Operation −4.1dBFS −4.1dBFS LMTH1-0 Limiter detection Level ZELMN Limiter zero crossing detection Enable Enable Zero crossing timeout period...
  • Page 80 [AK4675] The following registers should not be changed during ALC operation. These bits should be changed after ALC operation is finished by ALC bit = “0”. Each bit of LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN and RFST1-0. Example: Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Zero Crossing Timeout Period = 32ms@8kHz Limiter and Recovery Step = 1...
  • Page 81 [AK4675] Input Digital Volume (Manual Mode) The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below. 1. After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH1-0 and etc) 2.

  • Page 82: Band Equalizer

    [AK4675] 5-Band Equalizer The AK4675 has 5-Band Equalizer before DAC of Stereo CODEC. The center frequencies and cut/boost amount are the followings. • Center frequency: 100Hz, 250Hz, 1kHz, 3.5kHz, 10kHz (Note Note Note • Cut/Boost amount: –10.5dB ∼ +12dB, 1.5dB step Note 80: These are the frequencies when the sampling frequency is 44.1kHz.
  • Page 83 [AK4675] Digital Output Volume The AK4675 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the OVL7-0 and OVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or MUTE.
  • Page 84 [AK4675] Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by −∞ (“0”) during the cycle set by the OVTM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the value set by the OVL/R7-0 bits during the cycle set of the OVTM bit.
  • Page 85 [AK4675] Digital Volume Control for Recording of Received Voice (DATT-B) The AK4675 has a digital output volume control (DATT-B: 256 levels, 0.5dB step, Mute) for recording of received voice. The volume can be set by the BVL7-0 bits. The volume is included in front of an SRC-B block. The input data of SRC-B is changed from +12 to –115dB or MUTE.
  • Page 86 [AK4675] Digital Volume Control for B/T MIC Input (BIVOL) The AK4675 has a digital volume control (5 levels, 6dB step) for B/T mic input. The volume can be set by the BIV2-0 bits. The volume is included at SDTIB input. The input data is changed from 0 to –24dB. BIV2-0 Gain (default)
  • Page 87 [AK4675] SDOL1-0 and SDOR1-0 bits set the data mixing for each channel of SDTO from the data selected by Table 44 and SRC-B output data. SDOL1 SDOL0 SDTO Lch Lch Signal selected by Table 44 (default) SRC-B (Lch Signal selected by Table 44) + (SRC-B) Table 45.
  • Page 88 [AK4675] SRMXL1-0 and SRMXR1-0 bits set the data mixing for each channel of 5-band EQ from the data selected by Table 49/Table 50 and SVOLA output data. SRMXL1 SRMXL0 5-band EQ Lch Input Signal selected by Table 49 (default) SRC-B (Signal selected by Table 49) + (SRC-B)
  • Page 89 [AK4675] SBMX1-0 bits set the data mixing from SDTIA input and SVOLB output. The mixed data is output to SDTOB via DATT-C. SBMX1 SBMX0 DATT-C Input SDTIA (default) SVOLB (SDTIA) + (SVOLB) Table 57. SDTOB Mixing (N/A: Not available) When SDOBD bit is “1”, SDTOB output data can be disabled (fixed to “L”). SDOBD SDTOB Enable (Output)
  • Page 90 [AK4675] Analog Mixing: Single-ended Input (LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins) AK4675 supports analog mixing function from each line input to each line output (Figure 63). When the analog mixing is used, A/D converter is also available if PMADL or PMADR bit is “1”. When PMAINL1=PMAINR1=PMAINL2=PMAINR2=PMAINL3=PMAINR3=PMAINL4=PMAINR4=PMMICL=PMMICR bits = “1”, the input resistance of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins becomes 25kΩ...
  • Page 91 [AK4675] L1G1 bit L1G0 bit Gain (default) +6dB −6dB Table 60. LIN1/RIN1 (or IN1+/−) Mixing Gain (typ) (N/A: Not available) L2G1 bit L2G0 bit Gain (default) +6dB −6dB Table 61. LIN2/RIN2 (or IN2+/−) Mixing Gain (typ) (N/A: Not available) L3G1 bit L3G0 bit Gain (default)
  • Page 92 [AK4675] Stereo Line Output (LOUT1/ROUT1 pins) When DACL and DACR bits are “1”, Lch/Rch signal of DAC is output from the LOUT1/ROUT1 pins which is single-ended. When DACL and DACR bits are “0”, output signal is muted and LOUT1/ROUT1 pins output VCOM voltage.
  • Page 93 [AK4675] <Stereo Line Output Control Sequence (in case of using Pop Noise Reduction Circuit)> ( 2 ) ( 5 ) P M L O 1 b it P M R O 1 b it ( 1 ) ( 3 ) ( 4 ) ( 6 ) L O P S 1 b it...
  • Page 94 [AK4675] <Analog Mixing Circuit for LOUT1/ROUT1> DACL, DACR, LOM, LINL1, RINR1, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, LOOPL, LOOPR and LOOPM bits control each path switch. LINL1 bit LIN1 pin +6/0/−6dB LINL2 bit LIN2 pin +6/0/−6dB LINL3 bit LIN3 pin +6/0/−6dB LINL4 bit LIN4 pin...
  • Page 95 [AK4675] LINL1 bit +6/0/−6dB IN1+/− pins LINL2 bit LINL3 bit +6/0/−6dB IN3+/− pins LINL4 bit LOOPL bit LOUT1 pin +6/0/−6dB L1VL2-0 bits LOOPR bit x LOOPM bit MIC-Amp Lch DACL bit DATT Stereo DAC Lch DACR bit x LOM bit RINL1 bit RINR2 bit +6/0/−6dB...
  • Page 96 [AK4675] Receiver-Amp (RCP/RCN pins) When RCV bit = “1”, LOUT1/ROUT1 pins become RCP/RCN pins, respectively. Lch/Rch signal of DAC or LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the RCP/RCN pins which is BTL as (L+R) signal. The load impedance is 32Ω (min). When the PMLO1 = PMRO1 bits = “0”, the mono receiver output enters power-down mode and the output is Hi-Z.
  • Page 97 [AK4675] <Analog Mixing Circuit for Receiver Output> DACL, DACR, LINL1, RINR1, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, LOOPL and LOOPR bits control each path switch. When MDIF1/2/3/4 bits = “1”, RINR1/2/3/4 bits should be “0”. LINL1 bit LIN1 pin +6/0/−6dB LINL2 bit LIN2 pin +6/0/−6dB...
  • Page 98 [AK4675] LINL1 bit +6/0/−6dB IN1+/− pins LINL2 bit +6/0/−6dB IN2+/− pins LINL3 bit +6/0/−6dB IN3+/− pins LINL4 bit +6/0/−6dB IN4+/− pins LOOPL bit +6/0/−6dB RCP/RCN pins MIC-Amp Lch L1VL2-0 bits LOOPR bit +6/0/−6dB MIC-Amp Rch DACL bit DATT Stereo DAC Lch DACR bit DATT Stereo DAC Rch...
  • Page 99 [AK4675] <Analog Mixing Circuit for LOUT2S/ROUT2S> DACHL, DACHR, LOM2, LINH1, RINH1, LINH2, RINH2, LINH3, RINH3, LINH4, RINH4, LOOPHL, LOOPHR and LOOPM2 bits control each path switch. LINH1 bit LIN1 pin +6/0/−6dB LINH2 bit LIN2 pin +6/0/−6dB LINH3 bit LIN3 pin +6/0/−6dB LINH4 bit LIN4 pin...
  • Page 100 [AK4675] LINH1 bit +6/0/−6dB IN1+/− pins LINH2 bit LINH3 bit +6/0/−6dB IN3+/− pins LINH4 bit LOOPHL bit LOUT2S pin +6/0/−6dB LOOPHR bit x LOOPM2 bit MIC-Amp Lch DACHL bit DATT Stereo DAC Lch DACHR bit x LOM2 bit RINH1 bit RINH2 bit IN2+/−...
  • Page 101 [AK4675] Stereo Line Output 3 (LOUT3/ROUT3 pins) When DACSL and DACSR bits are “1”, Lch/Rch signal of DAC is output from the LOUT3/ROUT3 pins which is single-ended. When DACSL and DACSR bits are “0”, output signal is muted and LOUT3/ROUT3 pins output VCOM voltage.
  • Page 102 [AK4675] <Stereo Line Output 3 Control Sequence (in case of using Pop Noise Reduction Circuit)> ( 2 ) ( 5 ) P M L O 3 b it P M R O 3 b it ( 1 ) ( 3 ) ( 4 ) ( 6 ) L O P S 3 b it...
  • Page 103 [AK4675] <Analog Mixing Circuit for LOUT3/ROUT3> DACSL, DACSR, LOM3, LINS1, RINS1, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, LOOPSL, LOOPSR and LOM3 bits control each path switch. The summing gain for each path is 0dB (typ). LINS1 bit LIN1 pin +6/0/−6dB LINS2 bit LIN2 pin +6/0/−6dB...
  • Page 104 [AK4675] LINS1 bit +6/0/−6dB IN1+/− pins LINS2 bit LINS3 bit +6/0/−6dB IN3+/− pins LINS4 bit LOOPSL bit LOUT3 pin +6/0/−6dB L3VL1-0 bits LOOPSR bit x LOOPM3 bit MIC-Amp Lch DACSL bit DATT Stereo DAC Lch DACSR bit x LOM3 bit RINS1 bit RINS2 bit +6/0/−6dB...
  • Page 105 [AK4675] Full-differential Mono Line Output (LOP/LON pins) When LODIF bit = “1”, LOUT3/ROUT3 pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins which is full-differential as (L+R) signal. The load impedance is 10kΩ (min) for the LOP and LON pins, respectively. When the PMLO3 = PMRO3 bits = “0”, the mono line output enters power-down mode and the output is pulled-down to VSS1.
  • Page 106 [AK4675] <Analog Mixing Circuit for Mono Line Output> DACSL, DACSR, LINS1, RINS1, LINS2, RINS2, LINS3, RINS3, LINS4, RINS4, LOOPSL and LOOPSR bits control each path switch. The summing gain for each path is 0dB (typ). When MDIF1/2/3/4 bits = “1”, RINS1/2/3/4 bits should be “0”. LINS1 bit LIN1 pin +6/0/−6dB...
  • Page 107 [AK4675] LINS1 bit IN1+/ − pins +6/0/−6dB LINS2 bit IN2+/ − pins +6/0/−6dB LINS3 bit IN3+/ − pins +6/0/−6dB LINS4 bit IN4+/ − pins +6/0/−6dB LOOPSL bit +6/0/−6dB LOP/LON pins MIC-Amp Lch L3VL1-0 bits LOOPSR bit +6/0/−6dB MIC-Amp Rch DACSL bit DATT Stereo DAC Lch DACSR bit...
  • Page 108 [AK4675] Headphone Volume (LIN1A/RIN1A pins) The AK4675 has the mixing circuits for headphone amplifier. The each mixing circuit can be controlled independently. When all input paths are OFF, the mixing circuit outputs VCOMA voltage. The volume of each input pin can be controlled independently.
  • Page 109 [AK4675] Headphone-Amp (HPL/HPR pins) Power supply voltage for headphone amplifiers is applied from PVDDA and PVEE pins. The PVEE pin outputs the negative voltage generated by the internal charge pump circuit. The headphone amplifier is single-ended outputs and centered on 0V (VSS3A). Therefore, the capacitor for AC-coupling can be removed. The minimum load resistance is 16Ω.
  • Page 110 [AK4675] The headphone output is enabled when HPMTN bit is “1” and muted when HPMTN bit is “0”. PTS1-0 bits set the mute ON/OFF time when MOFF1 bit is “0”. When MOFF1 bit is “1”, the ON/OFF is switched immediately. When PMHPL and PMHPR bits are “0”, the headphone-amps are powered-down completely.

  • Page 111: Transition Time

    [AK4675] Charge Pump Circuit The charge pump operates by the output of a regulator which uses PVDDA voltage. The negative power supply (PVEE) for headphone amplifiers is generated from internal charge pump circuit. The internal charge pump circuit generates negative voltage from PVDDA voltage. The generated voltage (PVEE) is used to headphone amplifiers. When PMCP bit is set to “1”, the charge pump circuit is powered-up.
  • Page 112 [AK4675] Speaker-ALC Operation The ALC (Automatic Level Control) operation of speaker-amp output is executed by ALCA block when ALCA bit = “1”. When ALCA bit is “0”, the speaker volume depends on the setting value of SPGA5-0 bits. (1) ALC Limiter Operation During ALCA limiter operation, when either Lch or Rch exceeds the ALCA limiter detection level (LMTHA bit), the SPGA value (same value for Lch and Rch) is attenuated automatically by the ALCA limiter ATT step (LMATA1-0 bits).
  • Page 113 [AK4675] (2) ALCA Recovery Operation ALCA recovery operation waits for the WTMA2-0 bits to be set after completing ALCA limiter operation. If the input signal does not exceed “ALCA recovery waiting counter reset level” during the wait time, ALCA recovery operation is executed.
  • Page 114 [AK4675] REFA5-0 GAIN (dB) Step +19.5 +19.0 +18.5 +18.0 (default) +0.5 0.5dB −0.5 −11.0 −11.5 −12.0 Table 87. Reference Level at ALCA Recovery Operation MS0963-E-00 2008/05 - 114 -...
  • Page 115 [AK4675] (3) Example of ALCA Operation Table 88 shows the example of the ALCA setting. The ALCA starts from the value of SPGA5-0 bits. Register Name Comment Data Parameter −7.5dBV LMTHA Limiter detection Level ZELMNA Limiter Zero crossing Enable Limiter Zero Crossing Enable WTMA2-0 Recovery waiting period Typ.
  • Page 116 [AK4675] Speaker Volume (SPGA: Manual Mode) The speaker volume becomes manual mode when ALCA bit is “0”. This mode is used in the case shown below. 1. After exiting reset state, set-up the registers for ALCA operation (ZTMA1-0, LMTHA and etc). 2.
  • Page 117 [AK4675] Class-D Speaker-Amp The output signal from ALC block is converted by PWM and is outputted from the SPP/SPN pins by BLT. The signal of ALC block is input from the SPIN pin. A 0.1uF capacitor should be connected between the LOUT3 (ROUT3) pin and the SPIN pin in order to cancel DC offset of Line Out circuit.
  • Page 118 [AK4675] When PMSPL and PMSPR bits are set to “0”, the speaker block (ALC + Speaker-Amp) can be powered-down completely. In case of OSCN bit = “0”, the power-up/down time is 30ms (typ.) and 48ms (max.). In case of OSCN bit = “1”, the power-up/down time depends on MSEL bit setting and MCKIA frequency (Table 90).
  • Page 119 [AK4675] HP/SPK-Amp Block Power-Up/Down Sequence 1) HP-Amp Power Supply PDNA pin PMVCMA bit PMOSC bit PMMHL/R bit MCKIA Input Don’t care Don’t care PMCP bit PVEE pin PVEE ≥ 0s (11) PMV1 bit Input Volume Hi-Z VCOMA Hi-Z Output State PMHPL/R bits HPMTN bit MUTE...
  • Page 120 [AK4675] Headphone-Amp goes to mute state after the transition time set by PTS1-0 and MOFF1 bits. (10) Headphone-Amp power-down: PMHPL/R bits = “1” å “0” Headphone-Amp is powered-down immediately. (11) Power-down of Charge Pump, VCOMA and HP-Amp Mixer & Selector (and the internal clock oscillator in case of OSCN bit = “0”): PMCP = PMMHL = PMMHR = PMOSC = PMVCMA bits = “1”...
  • Page 121 [AK4675] 2) SPK-Amp (SPIN to SPP/SPN) Power Supply PDNA pin PMVCMA bit PMOSC bit Don’t care MCKIA Input Don’t care (9)≥ 500us (4)≥ 0s PMSPK bit Hi-Z Hi-Z SPIN pin VCOMA Hi-Z VCOMA (6) ≥ 1.6ms (6)≥ 1.6ms SPGA bits Default Default Default...
  • Page 122 [AK4675] (9) Once Speaker-Amp is powered-down, Speaker-Amp can be powered-up again at 500μs or more later in case of OSCN bit = “0”, at 1024/MCKIA (=500μs @ MCKI = 2.048MHz) or more later in case of OSCN bit = “1” & MSEL bit = “0”, 1536/MCKIA (=500μs @ MCKIA = 3.072MHz) or more later in case of OSCN bit = MSEL bit = “1”.
  • Page 123 [AK4675] System Clock (PCM I/F) A reference clock of PLLBT is selected among the input clocks to the SYNCA, BICKA, SYNCB or BICKB pin. The required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by PMPCM bit. Input frequency is selected by PLLBT3-0 bits (Table 95).
  • Page 124 [AK4675] a) PLLBT reference clock: SYNCA or BICKA pin The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output via the SYNCB and BICKB pins. AK4675 Phone Module 1fs2 SYNCA SYNC ≥ 16fs2 BICKA BICK SDTI...
  • Page 125 [AK4675] PCM I/F Master Mode/Slave Mode The PLLBT2 bit selects either master or slave mode (Table 99). When either PCM I/F A or PCM I/F B is set in slave mode, the other is set in master mode. (For example, when PCM I/F B is set in slave mode, PCM I/F A is set in master mode.) When the AK4675 is power-down mode (PDN pin = “L”) or PMPCM bit = “0”, each clock pins (SYNCA, BICKA, SYNCB, BICKB) of PCM I/F become a Hi-Z (Table...
  • Page 126 [AK4675] PCM I/F A & B Format The AK4675 supports dual PCM I/F (PCM I/F A & PCM I/F B) that supports 3 kind of I/F (16bit Linear, 8bit A-Law and 8bit μ-Law) independently (Table 101, Table 102). Mode LAWA1 LAWA0 Format 16bit Linear...
  • Page 127 [AK4675] MSBSA BCKPA Data Interface Format Figure MSB of SDTOA is output by the falling edge (“↓”) of SYNCA. MSB of SDTIA is latched by the falling edge (“↓”) of the BICKA just after the output timing of SDTOA’s Figure 91 MSB.
  • Page 128 [AK4675] 1/fs2 SYNCA BICKA (16bit Linear) SDTOA D15 D14 D13 D12 D11 D10 D9 D15 D14 SDTIA Don’t Care Don’t Care D15 D14 D13 D12 D11 D10 D9 D15 D14 (8bit A-Law/μ-Law) SDTOA SDTIA Don’t Care Don’t Care Figure 91. Timing of Short Frame Sync (MSBSA bit = “0”, BCKPA bit = “0”) 1/fs2 SYNCA BICKA...
  • Page 129 [AK4675] 1/fs2 SYNCA BICKA (16bit Linear) SDTOA D15 D14 D13 D12 D11 D10 D9 D15 D14 SDTIA Don’t Care Don’t Care D15 D14 D13 D12 D11 D10 D9 D15 D14 (8bit A-Law/μ-Law) SDTOA SDTIA Don’t Care Don’t Care Figure 94. Timing of Short Frame Sync (MSBSA bit = “1”, BCKPA bit = “1”) 1/fs2 SYNCA (Master)
  • Page 130 [AK4675] 1/fs2 SYNCA (Master) SYNCA (Slave) BICKA (16bit Linear) D15 D14 D13 D12 D11 D10 D9 D15 D14 SDTOA Don’t Care D15 D14 D13 D12 D11 D10 D9 Don’t Care D15 D14 SDTIA (8bit A-Law/μ-Law) SDTOA SDTIA Don’t Care Don’t Care Figure 97.
  • Page 131 [AK4675] SYNCA 11 12 13 14 15 0 1 2 3 11 12 13 14 15 BICKA (32fs2) SDTOA(o) 15 14 6 5 4 3 SDTIA(i) 15 14 7 6 5 4 3 2 1 0 Don't Care Don't Care 17 18 31 0 1 2 3 16 17 18...
  • Page 132 [AK4675] Phone Path MIC-Amp & ALC Stereo Separation 5-band Notch SDTO Lch SDTO Rch Audio SVOLA SDTI Lch DATT 5-band SDTI Rch SMUTE Receiver Headphone Speaker SRC-A SDTOA SVOLB Baseband I/F A SDTIA SRC-B DATT-B DATT-C SDTOB SDTIB BIVOL I/F B Phone Call TX Phone Call TX Recording Phone Call Side Tone...
  • Page 133 [AK4675] MIC-Amp & ALC Stereo Separation 5-band Notch SDTO Lch SDTO Rch Audio SVOLA SDTI Lch DATT 5-band SDTI Rch SMUTE Receiver Headphone Speaker SRC-A SDTOA SVOLB Baseband I/F A SDTIA SRC-B DATT-B DATT-C SDTOB SDTIB BIVOL I/F B Phone Call TX Phone Call TX Recording Phone Call Side Tone Phone Call RX...

  • Page 134: General Purpose Output

    [AK4675] General Purpose Output The AK4675 has General Purpose Output Pin (GPO) to control the external component. In case of GPOM1 bit = “0”, the GPO1 pin goes to “H” at GPOE1 bit = “1”. GPOE1 bit GPO1 pin (default) Table 109.
  • Page 135 [AK4675] SAR 10bit ADC The AK4675 incorporates a 10-bit successive approximation resistor A/D converter for DC measurement. The A/D converter output is a straight binary format as shown in Table 112: Input Voltage Output Code AVDD 3FFH (AVDD−1.5LSB) 3FEH (AVDD−2.5LSB) (AVDD−1.5LSB) 0.5LSB 1.5LSB...

  • Page 136: Serial Control Interface

    [AK4675] ATT Circuit for Battery Monitor When BATCPU bit = “1”, the input voltage for the VBATIN pin is divided by the internal resistors R1 (7.5k) and R2 (2.5k). The VBATO pin outputs the internally divided voltage. When BATCPU bit = “0”, the VBATO pin goes to Hi-Z. This block can operate even if PMVCMA=PMOSC bits = “0”.
  • Page 137 [AK4675] The AK4675 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4675 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred.
  • Page 138 [AK4675] (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4675. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 7-bit address counter is incremented by one, and the next data is automatically taken into the next address.
  • Page 139 [AK4675] start condition stop condition Figure 111. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER clock pulse for acknowledgement START CONDITION Figure 112. Acknowledge on the I C-Bus data line change stable;...
  • Page 140 [AK4675] Register Map (CODEC & SRC Blocks) Addr Register Name AD/DA Power Management PMDAR PMDAL PMADR PMADL PMMICR PMMICL PMMP PMVCM PLL Mode Select 0 PLL3 PLL2 PLL1 PLL0 PLL Mode Select 1 BTCLK BCKO MCKO PMPLL Format Select SDOD MSBS BCKP DIF1...
  • Page 141 [AK4675] Addr Register Name Digital Filter Select 2 Reserved E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1 E1A0 E1 Co-efficient 1 E1A15 E1A14 E1A13 E1A12 E1A11 E1A10 E1A9 E1A8 E1 Co-efficient 2 E1B7 E1B6 E1B5 E1B4 E1B3 E1B2 E1B1 E1B0 E1 Co-efficient 3...
  • Page 142 [AK4675] Register Definitions (CODEC & SRC Blocks) Addr Register Name AD/DA Power Management PMDAR PMDAL PMADR PMADL PMMICR PMMICL PMMP PMVCM Default PMVCM: VCOM Power Management 0: Power down (default) 1: Power up When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only when all power management bits are “0”.
  • Page 143 [AK4675] Addr Register Name PLL Mode Select 0 PLL3 PLL2 PLL1 PLL0 Default PLL3-0: PLL Reference Clock Select (Table Default: “0110”(MCKI pin, 12MHz) FS3-0: Sampling Frequency Select (See Table 5 Table 6) and MCKI Frequency Select (Table FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. Addr Register Name PLL Mode Select 1...
  • Page 144 [AK4675] Addr Register Name Format Select SDOD MSBS BCKP DIF1 DIF0 Default DIF1-0: Audio Interface Format (Table Default: “10” (Left jutified) BCKP: BICK Polarity at DSP Mode (Table “0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default) “1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
  • Page 145 [AK4675] Addr Register Name MIC Amp Gain MGNR3 MGNR2 MGNR1 MGNR0 MGNL3 MGNL2 MGNL1 MGNL0 Default MGNL3-0: MIC-Amp Lch Gain Control (Table Default: “0101” (0dB) MGNR3-0: MIC-Amp Rch Gain Control (Table Default: “0101” (0dB) Addr Register Name Mixing Power Management 0 DTMIC PMLOOPR PMLOOPL...
  • Page 146 [AK4675] Addr Register Name Mixing Power Management 1 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMAINR1 PMAINL1 Default PMAINL1: LIN1 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINR1: RIN1 Mixing Circuit Power Management 0: Power down (default) 1: Power up PMAINL2: LIN2 Mixing Circuit Power Management 0: Power down (default)
  • Page 147 [AK4675] Addr Register Name LOUT1 Signal Select L1G1 L1G0 LOOPL LINL4 LINL3 LINL2 LINL1 DACL Default DACL: Switch Control from DAC Lch to LOUT1 0: OFF (default) 1: ON When PMLO1 bit is “1”, DACL bit is enabled. When PMLO1 bit is “0”, the LOUT1 pin goes to VSS1. LINL1: Switch Control from LIN1 to LOUT1 0: OFF (default) 1: ON...
  • Page 148 [AK4675] Addr Register Name ROUT1 Signal Select L2G1 L2G0 LOOPR RINR4 RINR3 RINR2 RINR1 DACR Default DACR: Switch Control from DAC Rch to ROUT1 0: OFF (default) 1: ON When PMRO1 bit is “1”, DACR bit is enabled. When PMRO1 bit is “0”, the ROUT1 pin goes to VSS1. RINR1: Switch Control from RIN1 to ROUT1 0: OFF (default) 1: ON...
  • Page 149 [AK4675] Addr Register Name LOUT2S Signal Select L3G1 L3G0 LOOPHL LINH4 LINH3 LINH2 LINH1 DACHL Default DACHL: Switch Control from DAC Lch to LOUT2S 0: OFF (default) 1: ON LINH1: Switch Control from LIN1 to LOUT2S 0: OFF (default) 1: ON LINH2: Switch Control from LIN2 to LOUT2S 0: OFF (default) 1: ON...
  • Page 150 [AK4675] Addr Register Name ROUT2S Signal Select L4G1 L4G0 LOOPHR RINH4 RINH3 RINH2 RINH1 DACHR Default DACHR: Switch Control from DAC Rch to ROUT2S 0: OFF (default) 1: ON RINH1: Switch Control from RIN1 to ROUT2S 0: OFF (default) 1: ON RINH2: Switch Control from RIN2 to ROUT2S 0: OFF (default) 1: ON...
  • Page 151 [AK4675] Addr Register Name LOUT3 Signal Select LPG1 LPG0 LOOPSL LINS4 LINS3 LINS2 LINS1 DACSL Default DACSL: Switch Control from DAC Lch to LOUT3 0: OFF (default) 1: ON When PMLO3 bit is “1”, DACSL bit is enabled. When PMLO3 bit is “0”, the LOUT3 pin goes to VSS1. LINS1: Switch Control from LIN1 to LOUT3 0: OFF (default) 1: ON...
  • Page 152 [AK4675] Addr Register Name ROUT3 Signal Select LOOPSR RINS4 RINS3 RINS2 RINS1 DACSR Default DACSR: Switch Control from DAC Rch to ROUT3 0: OFF (default) 1: ON When PMRO3 bit is “1”, DACR bit is enabled. When PMRO3 bit is “0”, the ROUT3 pin goes to VSS1. RINS1: Switch Control from RIN1 to ROUT3 0: OFF (default) 1: ON...
  • Page 153 [AK4675] Addr Register Name LOUT1 Power Management LOOPM LOPS1 PMRO1 PMLO1 Default PMLO1: LOUT1 Power Management 0: Power down (default) 1: Power up PMRO1: ROUT1 Power Management 0: Power down (default) 1: Power up LOPS1: LOUT1/ROUT1 Power Save Mode 0: Normal Operation (default) 1: Power Save Mode LOM: Mono Mixing from DAC to LOUT1/ROUT1 0: Stereo Mixing (default)
  • Page 154 [AK4675] Addr Register Name LOUT2S Power Management PMRO2S PMLO2S LOOPM2 LOM2 Default LOM2: Mono Mixing from DAC to LOUT2S/ROUT2S 0: Stereo Mixing (default) 1: Mono Mixing LOOPM2: Mono Mixing from MIC-Amp to LOUT2S/ROUT2S 0: Stereo Mixing (default) 1: Mono Mixing PMLO2S: LOUT2S MIX-Amp Power Management 0: Power down (default) 1: Power up...
  • Page 155 [AK4675] Addr Register Name LODIF LOUT3 Power Management L3VL1 L3VL0 LOOPM3 LOM3 LOPS3 PMRO3 PMLO3 Default PMLO3: LOUT3 Power Management 0: Power down (default) 1: Power up PMRO3: ROUT3 Power Management 0: Power down (default) 1: Power up LOPS3: LOUT3/ROUT3 Power Save Mode 0: Normal Operation (default) 1: Power Save Mode LOM3: Mono Mixing from DAC to LOUT3/ROUT3...
  • Page 156 [AK4675] Addr Register Name Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 Default IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (Table Default: “91H” (0dB) Addr Register Name ALC Reference Select...
  • Page 157 [AK4675] Addr Register Name ALC Mode Control ZELMN LMAT1 LMAT0 RGAIN1 RGAIN0 LMTH1 LMTH0 Default LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table Default: “00” RGAIN1-0: ALC Recovery GAIN Step (Table Default: “00” LMAT1-0: ALC Limiter ATT Step (Table Default: “00”...
  • Page 158 [AK4675] Addr Register Name Mode Control 2 SRA1 SRA0 BIV2 BIV1 BIV0 SMUTE OVTM OVOLC Default OVOLC: Output Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When OVOLC bit = “1”, OVL7-0 bits control both Lch and Rch volume level, while register values of OVL7-0 bits are not written to OVR7-0 bits.
  • Page 159 [AK4675] Addr Register Name Digital Filter Select FIL3 HPFAD PFSEL Default : Signal Select of Programmable Filter Block (Table 43.) PFSEL 0: ADC Output Data (default) 1: SDTI Input Data HPFAD: HPF Control of ADC 0: OFF 1: ON (default) When HPFAD bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled.
  • Page 160 [AK4675] Addr Register Name FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0 FIL3 Co-efficient 1 F3AS F3A13 F3A12 F3A11 F3A10 F3A9 F3A8 FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0 FIL3 Co-efficient 3 F3B13 F3B12 F3B11 F3B10...
  • Page 161 [AK4675] Addr Register Name Digital Filter Select 2 Default EQ1: Equalizer 1 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”, EQ1 block is through (0dB).
  • Page 162 [AK4675] Addr Register Name E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1 E1A0 E1 Co-efficient 1 E1A15 E1A14 E1A13 E1A12 E1A11 E1A10 E1A9 E1A8 E1 Co-efficient 2 E1B7 E1B6 E1B5 E1B4 E1B3 E1B2 E1B1 E1B0 E1 Co-efficient 3 E1B15 E1B14 E1B13...
  • Page 163 [AK4675] Addr Register Name EQ Control 250Hz/100Hz EQB3 EQB2 EQB1 EQB0 EQA3 EQA2 EQA1 EQA0 EQ Control 3.5kHz/1kHz EQD3 EQD2 EQD1 EQD0 EQC3 EQC2 EQC1 EQC0 Default Addr Register Name EQ Control 10kHz EQE3 EQE2 EQE1 EQE0 Default EQA3-0: Select the boost level of 100Hz EQB3-0: Select the boost level of 250Hz EQC3-0: Select the boost level of 1kHz EQD3-0: Select the boost level of 3.5kHz...
  • Page 164 [AK4675] Addr Register Name PCM I/F Control 0 GPOM2 GPOE2 PLLBT2 PLLBT1 PLLBT0 PMPCM PMSRB PMSRA Default PMSRA: SRC-A Power Management 0: Power down (default) 1: Power up PMSRB: SRC-B Power Management 0: Power down (default) 1: Power up PMPCM: PCM I/F Power Management 0: Power down (default) 1: Power up PLLBT2-0: PLLBT Reference Clock Select...
  • Page 165 [AK4675] Addr Register Name PCM I/F Control 2 SDOAD BCKO2 MSBSA BCKPA LAWA1 LAWA0 FMTA1 FMTA0 Default FMTA1-0: PCM I/F A Format (Table 103) Default: “00” (Mode 0) LAWA1-0: PCM I/F A Mode (Table 101) Default: “00” (Mode 0) BCKPA: BICKA Polarity of PCM I/F A (Table 105) “0”: SDTOA is output by the rising edge (“↑”) of BICKA and SDTIA is latched by the falling edge (“↓”).
  • Page 166 [AK4675] Addr Register Name Digital Volume B Control BVL7 BVL6 BVL5 BVL4 BVL3 BVL2 BVL1 BVL0 Default BVL7-0: Digital Volume B (Table Default: “18H” (0dB) Addr Register Name Digital Volume C Control CVL7 CVL6 CVL5 CVL4 CVL3 CVL2 CVL1 CVL0 Default CVL7-0: Digital Volume B (Table...
  • Page 167 [AK4675] Addr Register Name SAR ADC Control GPOM1 GPOE1 PMSAD Default PMSAD: 10bit ADC Power Management “0”: Power down (default) “1”: Power up A1-0: SAR ADC Measurement Mode (Table 113) Default: “00” (SAIN1) GPOE1: General Purpose Output 1 Enable at GPOM1 bit = “1” “0”: GPO pin = “L”...
  • Page 168 [AK4675] Register Map (HP/SPK-Amp Blocks) Addr Register Name Power Management 0 PMCP PMMHR PMMHL PMHPR PMHPL PMOSC PMVCMA Power Management 1 PMSPK GDDLY Power Management 2 PMV1 Mode Control 0 THDET Lch Headphone Mixer HPLR1 HPLL1 Rch Headphone Mixer HPRR1 HPRL1 Reserved Reserved...
  • Page 169 [AK4675] Register Definitions (HP/SPK-Amp Blocks) Addr Register Name Power Management 0 PMMHR PMMHL PMHPR PMHPL PMCP PMOSC PMVCMA Default PMVCMA: Power Management for VCOM and Regulator which used for Headphone-Amp 0: Power OFF (default) 1: Power ON PMOSC: I Power Management for Internal Oscillator 0: Power OFF (default) 1: Power ON PMCP: Power Management for Charge Pump Circuit...
  • Page 170 [AK4675] Addr Register Name Power Management 1 GDDLY PMSPK Default PMSPK: Power Management for Speaker-Amp 0: Power OFF (default) 1: Power ON When PMSP bit is “0”, the SPP pin and SPN pin become Hi-Z. GDDLY: Gate driver delay setting for dulling output wave of Class-D 0: 15ns (default) 1: 60ns Delay increase, EMI improve, Efficiency down when “0”...
  • Page 171 [AK4675] Addr Register Name Mode Control 0 THDET Default THDET: Thermal Shutdown Detection 0: Normal Operation (default) 1: Thermal Shutdown Addr Register Name Lch Headphone Mixer HPLR1 HPLL1 Rch Headphone Mixer HPRR1 HPRL1 Default Input Mixers: (Figure 0: OFF (default) 1: ON Addr Register Name...
  • Page 172 [AK4675] Addr Register Name Mode Control 1 MOFF PTS1 PTS0 Default PTS1-0: Headphone-Amp Mute ON/OFF Transition Time Default: “00”; typ. 16.4ms (Table MOFF: Soft transition for changing HPMTN bit 0: Enable (default) 1: Disable Addr Register Name Headphone PGA Control HPMTN HPGA4 HPGA3 HPGA2 HPGA1 HPGA0 Default...
  • Page 173 [AK4675] Addr Register Name ALCA Mode Control 2 ZTMA1 ZTMA0 WTMA2 WTMA1 WTMA0 Default WTMA2-0: ALCA Recovery Waiting Period Default: “101”, typ. 524.8ms (@OSCN bit = “0”) (Table ZTMA1-0: ALCA Zero Crossing Timeout Period Default: “01”, typ. 32.8ms (@ OSCN bit = “0”) (Table Addr Register Name...

  • Page 174: System Design

    [AK4675] SYSTEM DESIGN Figure 114 shows the system connection diagram for the AK4675. An evaluation board [AKD4675] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Condition: Internal Full-differential Mic, External pseudo differential Mic, Receiver Output, I²C mode; Battery Monitor is used;...
  • Page 175 [AK4675] Notes: - VSS1, VSS2, VSS3, VSS4, VSS1A, VSS2A and VSS3A of the AK4675 must be distributed separately from the ground of external controllers. - All digital input pins msut not be left floating. - When the AK4675 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of the VCOC pin is not needed. - When the AK4675 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of the VCOC pin is shown in Table - When the AK4675 is in master mode, the LRCK and BICK pins are floating before M/S bit is changed to “1”.

  • Page 176: Grounding And Power Supply Decoupling

    [AK4675] 1. Grounding and Power Supply Decoupling The AK4675 requires careful attention to power supply and grounding arrangements. AVDD, PVDD, SAVDD, DVDD, TVDD2, TVDD3, AVDDA, PVDDA, SVDDA and TVDDA are usually supplied from the system’s analog supply. TVDDA must be connected to DVDD. If AVDD, PVDD, SAVDD, DVDD, TVDD2, AVDDA, PVDDA and SVDDA are supplied separately, the power-up sequence is not critical.
  • Page 177 [AK4675] PACKAGE 5.5 ± 0.1 83 - φ 0.3 ± 0.05 φ 0.05 8 7 6 5 4 3 10 9 0.08 S ̈ Material & Lead finish Package molding compound: Epoxy Interposer material: BT resin Solder ball material: SnAgCu MS0963-E-00 2008/05 - 177 -...

  • Page 178: Revision History

    [AK4675] MARKING 4675 XXXXX XXXXX: Date code identifier (5digits) Pin #1 indication REVISION HISTORY Date (YY/MM/DD) Revision Reason Page Contents 08/05/23 First Edition IMPORTANT NOTICE ” These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products.

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