AKM AK4537 Manual

16-bit '6 stereo codec with mic/hp/spk-amp ak4537

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ASAHI KASEI

The AK4537 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo

CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits

include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4537 is available in a

52-QFN, utilizing less board space than competitive offerings.

MS0202-E-04

Downloaded from

Elcodis.com

electronic components distributor

16-Bit '6 Stereo CODEC with MIC/HP/SPK-AMP

1. Resolution : 16bits

2. Recording Function

x Stereo Mic Input

x Stereo Line Input

x 1

MIC Amplifier : +20dB or 0dB

x 2

Amplifier with ALC

+27.5dB a -8dB, 0.5dB Step (MIC input)

+12dB a -23.5dB, 0.5dB Step (LINE input)

x ADC Performance : S/(N+D) : 79dB, DR, S/N : 83dB (MIC input)

3. Playback Function

x Digital De-emphasis Filter (tc=50/15Ps, fs=32kHz, 44.1kHz, 48kHz)

x Digital Volume (0dB a -127dB, 0.5dB Step, Mute)

x Stereo Headphone-Amp

- S/(N+D) : 70dB, S/N : 90dB

- Output Power : 15mW@16: (HVDD=3.3V)

- Click Noise Free at Power ON/OFF

x Mono Speaker-Amp with ALC

- S/(N+D) : 64dB@150mW, S/N : 90dB

- BTL Output

- Output Power : 400mW@8: (BEEP Input, HVDD=3.3V)

x Mono and Stereo Beep Inputs

x Mono Line Output

- Differential Output

- Performance : S/(N+D) : 89dB, S/N : 95dB

x Stereo Line Output

- Performance : S/(N+D) : 88dB, S/N : 92dB

4. Power Management

5. Master Clock

(1) PLL Mode

x Frequencies : 11.2896MHz, 12MHz and 12.288MHz

x Input Level : CMOS

(2) External Clock Mode

x Frequencies : 2.048MHz a 12.288MHz

6. Output Master Clock Frequencies : 32fs/64fs/128fs/256fs

7. Sampling Rate :

(1) PLL mode

x 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

(2) External Clock mode

x 8kHz a 48kHz

8. Control mode: 4-wire Serial / I

9. Master/Slave mode

GENERAL DESCRIPTION

FEATURES

S/(N+D) : 88dB, DR, S/N : 91dB (LINE input)

300mW@8: (MIN Input, ALC2=OFF, HVDD=3.3V)

C Bus

- 1 -

[AK4537]

AK4537

2005/04

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Summary of Contents for AKM AK4537

Page 1 16-Bit '6 Stereo CODEC with MIC/HP/SPK-AMP GENERAL DESCRIPTION The AK4537 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4537 is available in a 52-QFN, utilizing less board space than competitive offerings.
Page 2 ASAHI KASEI [AK4537] 10. Audio Interface Format : MSB First, 2’s compliment x ADC : I S, 16bit MSB justified x DAC : I S, 16bit MSB justified, 16bit LSB justified 11. Ta = -10 a 70qC 2.4V a 3.6V (typ. 3.3V) 12.
Page 3 ASAHI KASEI [AK4537] „ Ordering Guide 10 a +70qC AK4537VN 52pin QFN (0.4mm pitch) AKD4537 Evaluation board for AK4537 „ Pin Layout 52 51 50 49 48 47 46 45 44 43 42 MUTET MICOUTL MICOUTR EXT/MICR HVSS HVDD INT/MICL...
Page 4 ASAHI KASEI [AK4537] „ Comparison with AK4534 1. Function Function AK4534 AK4537 Line Input Yes (Stereo) Mic Input Mono Stereo IPGA Mono Stereo Stereo Line Output SPK-Amp Gain Select MOUT Gain Select Path from IPGA Lch to Analog Output 2. Pin...
Page 5 ASAHI KASEI [AK4537] PIN/FUNCTION No. Pin Name Function MICOUTL MIC-Amp Lch Output Pin MICOUTR MIC-Amp Rch Output Pin External Microphone Input Pin (Mono Input) (PMMICR bit = “0”) MICR Stereo Microphone Rch Input Pin (PMMICR bit = “1”) MIC Power Supply Pin for External Microphone / Stereo Microphone Rch...
Page 6 ASAHI KASEI [AK4537] No. Pin Name Function No Connect. This pin should be left floating. DVDD Digital Power Supply Pin DVSS Digital Ground Pin X’tal Output Pin X’tal Input Pin MCKI External Master Clock Input Pin Master / Slave Mode Pin “H”...
Page 7 Note 3. The power up sequence between AVDD, DVDD, HVDD and PVDD is not critical. It is recommended that DVDD and PVDD are the same voltage as AVDD in order to reduce the current at power down mode. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0202-E-04 2005/04...
Page 8 ASAHI KASEI [AK4537] ANALOG CHARACTERISTICS (Ta=25qC; AVDD, DVDD, PVDD, HVDD=3.3V; AVSS=DVSS=PVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz a 20kHz; unless otherwise specified) Parameter Units MIC Amplifier: Input Resistance Gain (MGAIN bit = “0”) (MGAIN bit = “1”) MIC Power Supply:...
Page 9 ASAHI KASEI [AK4537] Units Parameter =20k:, DAC o MOUT+/MOUT- Mono Line Output Characteristics: R Output Voltage (Note 10) MOGN=1, -17dB 0.31 3.56 3.96 4.36 MOGN=0, +6dB S/(N+D) (-3dBFS) MOGN=1, -17dB dBFS MOGN=0, +6dB dBFS (A-weighted) MOGN=1, -17dB MOGN=0, +6dB Load Resistance...
Page 10 ASAHI KASEI [AK4537] Units Parameter BEEP Input: BEEPL, BEEPR, BEEPM pin Maximum Input Voltage (Note 13) 1.98 Feedback Resistance Mono Input: MIN pin Maximum Input Voltage (Note 14) 1.98 Input Resistance (Note 15) =10k:, DAC o MIX o MOUT2 Mono Output: R...
Page 11 ASAHI KASEI [AK4537] FILTER CHARACTERISTICS (Ta=10 a 70qC; AVDD, DVDD, PVDD, HVDD=2.4 a 3.6V; fs=44.1kHz; DEM=OFF) Parameter Symbol Units ADC Digital Filter (Decimation LPF): r0.1dB Passband (Note 22) 17.4 1.0dB 20.0 3.0dB 21.1 Stopband 27.0 r0.1 Passband Ripple Stopband Attenuation...
Page 12 ASAHI KASEI [AK4537] DC CHARACTERISTICS (Ta=10 a 70qC; AVDD, DVDD, PVDD, HVDD=2.4 a 3.6V) Parameter Symbol Units High-Level Input Voltage 70%DVDD Low-Level Input Voltage 30%DVDD Input Voltage at AC Coupling (Note 25) 50%DVDD High-Level Output Voltage (Iout=200PA) DVDD0.2 Low-Level Output Voltage...
Page 13 Note 29. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 30. The AK4537 can be reset by the PDN pin = “L”. Note 31. This is the count of LRCK “n” from the PMADL or PMADR bit = “1”.
Page 14 ASAHI KASEI [AK4537] „ Timing Diagram 1/fCLK MCLK tCLKH tCLKL 1/fs LRCK tBCK BICK tBCKH tBCKL fMCK MCKO 50%DVDD dMCK dMCK Figure 3. Clock Timing 1/fCLK tACW tACW 1000pF MCKI Input Measurement Point 100k: AGND AGND Figure 4. MCKI AC Coupling Timing...
Page 15 ASAHI KASEI [AK4537] LRCK tBLR tLRB BICK tLRS tBSD SDTO 50%DVDD tSDS tSDH SDTI Figure 5. Audio Interface Timing (Slave mode) LRCK tMBLR dBCK BICK 50%DVDD tBSD SDTO 50%DVDD tSDS tSDH SDTI Figure 6. Audio Interface Timing (Master mode) MS0202-E-04...
Page 16 ASAHI KASEI [AK4537] tCSS tCCKL tCCKH CCLK tCDS tCDH CDTI Hi-Z CDTO Figure 7. WRITE/READ Command Input Timing tCSW tCSH CCLK CDTI Hi-Z CDTO Figure 8. WRITE Data Input Timing MS0202-E-04 2005/04 - 16 - Downloaded from Elcodis.com electronic components distributor...
Page 17 ASAHI KASEI [AK4537] CCLK x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x...
Page 18 ASAHI KASEI [AK4537] tBUF tLOW tHIGH tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO Stop Start Start Stop Figure 11. I C Bus Mode Timing tPDV x x x x x x x x x x x x x x x x x x...
Page 19 „ Master Clock Source The AK4537 requires a master clock (MCLK). This master clock is input to the AK4537 by connecting a X’tal oscillator to XTI and XTO pins or by inputting an external CMOS-level clock to the XTI pin or by inputting an external clock that is greater than 50% of the DVDD level to the XTI pin through a capacitor.
Page 20 ASAHI KASEI [AK4537] (2) External Clock Direct Input External Clock MCKPD = "0" 25k: PMXTL = "0" AK4537 Figure 14. External Clock mode (Input : CMOS Level) Note: This clock level must not exceed DVDD level. (3) AC Coupling Input...
Page 21 (LRCK). The phase between these clocks does not matter. LRCK and BICK must be present whenever the AK4537 is operating (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic.
Page 22 LRCK and BICK are output from the AK4537 in master mode. The clock to the MCKI pin must not stop during normal operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If this clock is not provided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic.
Page 23 The M/S pin selects either master or slave modes. M/S pin = “H” selects master mode and “L” selects slave mode. The AK4537 outputs MCKO, BICK and LRCK in master mode. The AK4537 outputs only MCKO in slave mode, while BICK and LRCK must be input separately.
Page 24 All data formats can be used in both master and slave modes. LRCK and BICK are output from AK4537 in master mode, but must be input to AK4537 in slave mode. If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, 1 at 16bit data is converted to 1 at 8-bit data.
Page 25 ASAHI KASEI [AK4537] LRCK x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x...
Page 26 ASAHI KASEI [AK4537] „ MIC Gain Amplifier AK4537 has a Gain Amplifier for Microphone input. This gain is 0dB or 20dB, selected by the MGAIN bit (Table 14). The typical input impedance is 30k:. MGAIN bit Input Gain +20dB Default Table 14.
Page 27 [2] ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4537 will allow both Lch and Rch signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation.
Page 28 ASAHI KASEI [AK4537] [3] Example of ALC1 Operation Table 15 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB. fs=8kHz fs=16kHz fs=44.1kHz Register Name Comment Data Operatio Data Operatio Data Operatio LMTH...
Page 29 ASAHI KASEI [AK4537] „ De-emphasis Filter The AK4537 includes the digital de-emphasis filter (tc = 50/15Ps) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 16). DEM1 DEM0 Mode 44.1kHz Default 48kHz 32kHz Table 16. De-emphasis Control „...
Page 30 „ Digital Attenuator The AK4537 has a channel-independent digital attenuator (256 levels, 0.5dB step, Mute). The attenuation level of each channel can be set by the ATTL/R7-0 bits. When the DATTC bit = “1”, the ATTL7-0 bits control both Lch and Rch attenuation levels.
Page 31 ASAHI KASEI [AK4537] „ BEEP Input When the PMBPS bit is set to “1”, the stereo beep input is powered up. And when the BPSHP bit is set to “1”, the input signals from the BEEPL and BEEPR pins are mixed to Headphone outputs. When the BPSSP bit is set to “1”, the signal of (BEEPL + BEEPR)/2 is input to Speaker-amp.
Page 32 ASAHI KASEI [AK4537] „ Headphone Output Power supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the HVDD/2 voltage. The Headphone output load resistance is min.20:. When the PMHPL and PMHPR bits are “0”, the common voltage of Headphone-amp falls and the outputs (HPL and HPR pins) go to “L”...
Page 33 ASAHI KASEI [AK4537] The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 19 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance R is 16:. Output powers are shown at HVDD = 2.7, 3.0 and 3.3V. The output voltage of headphone is 0.6 x AVDD (Vpp).
Page 34 SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4537 is powered down, pop noise can be also reduced by first entering power-save-mode.
Page 35 ASAHI KASEI [AK4537] Using BEEPL and BEEPR pins AK4537 r 30% BPSSP SPK-Amp 45%AVDD r 30% BPSSP 45%AVDD MOUT2 0.068u BEEPL BEEPR Figure 30. Connection example for 400mW output using BEEPL and BEEPR pins (SPKG bit = “1”) Note) MOUT2 output is recommended to be AC coupled to avoid amplified DC offset of common voltage of MOUT2 and BEEP-Amp is output via BTL Speaker-Amp (that means stand-by current is increased).
Page 36 ASAHI KASEI [AK4537] „ Stereo Line Output (LOUT/ROUT pins) MIC In 0dB/+20dB IPGA Lch “MICL” “DAHS” LOUT pin ATT+DAC ROUT pin Figure 31. Stereo Line Output When DAHS bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When MICL bit is “1”, Lch signal of IPGA is output from LOUT/ROU pins.
Page 37 ASAHI KASEI [AK4537] „ ALC2 Operation (ALC2 bit = “1”) Input resistance of the ALC2 is 24k: (typ) and centered around VCOM voltage, and the input signal level is –3.1dBV. (see Figure 33 and Figure 34. 0dBV=1Vrms=2.828Vpp) The limiter detection level is proportional to HVDD. The output level is limited by the ALC2 circuit when the input signal exceeds –5.2dBV (=FS-1.9dB@HVDD=3.3V).
Page 38 ASAHI KASEI [AK4537] 3.0dBV(250mW@8ohm) FS-2.1dB = -5.2dBV 1.0dBV 0dBV +8.2dB -3.3dBV -3.3dBV +8.2dB -1.9dB Full-differential -3.0dBV +2.2dB Single-ended -5.0dBV +2.2dB -8dB +4.1dB -10dBV -11.3dBV +8.1dB FS-12dB -15.3dBV -15.3dBV FS-4.1dB = -7.2dBV +16.1dB -20dBV -8dB -23.3dBV -30dBV DATT ALC2 SPK-AMP Figure 34. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT=8.0dB, SPKG bit= “1”, ALC2= “1”)
Page 39 ASAHI KASEI [AK4537] „ Serial Control Interface (1) 4-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written by using the 4-wire µP interface pins (CSN, CCLK, CDTI and CDTO). The data on this interface consists of a 2-bit Chip address, Read/Write, Register address (MSB first, 5bits) and Control data (MSB first, 8bits).
Page 40 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1 and CAD0 pins) set these device address bits (Figure 37). If the slave address matches that of the AK4537, the AK4537 generates an acknowledge and the operation is executed.
Page 41 (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4537. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
Page 42 ASAHI KASEI [AK4537] start condition stop condition Figure 42. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER clock pulse for acknowledgement START CONDITION Figure 43. Acknowledge on the I C-Bus...
Page 43 ASAHI KASEI [AK4537] „ Register Map Addr Register Name Power Management 1 PMVCM PMBPS PMBPM PMLO PMMO PMIPGL PMMICL PMADL Power Management 2 MCKPD PMXTL PMPLL SPKG PMSPK PMHPL PMHPR PMDAC Signal Select1 MOGN PSMO DAMO MICM BPSSP BPMSP ALCS...
Page 44 ASAHI KASEI [AK4537] „ Register Definitions Addr Register Name Power Management 1 PMVCM PMBPS PMBPM PMLO PMMO PMADL PMIPGL PMMICL Default PMADL: ADC Lch Block Power Control 0: Power down (Default) 1: Power up When the PMADL or PMADR bit changes from “0” to “1”, the initialization cycle (2081/fs=47.2ms @44.1kHz) starts.
Page 45 ASAHI KASEI [AK4537] PMVCM: VCOM Block Power Control 0: Power down (Default) 1: Power up Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are powered down. When all bits except MCKPD bit are “0” in the 00H, 01H and 10H addresses, all blocks are powered down. The register values remain unchanged.
Page 46 ASAHI KASEI [AK4537] Addr Register Name Signal Select 1 MOGN PSMO DAMO MICM BPSSP BPMSP ALCS MOUT2 Default MOUT2: MOUT2 Output Enable (Mixing = (L+R)/2) 0: OFF (Default) 1: ON When the MOUT2 bit = “0”, the MOUT2 pin outputs VCOM voltage. The MOUT2 pin outputs signal at the MOUT2 bit = “1”.
Page 47 ASAHI KASEI [AK4537] DAHS MOUT2 ALCS ALC2 BPMSP BEEPM BPSSP BEEPL BEEPR Figure 45. Speaker-amp switch control MS0202-E-04 2005/04 - 47 - Downloaded from Elcodis.com electronic components distributor...
Page 48 ASAHI KASEI [AK4537] Addr Register Name Signal Select 2 DAHS PSLO MICL BPSHP BPMHP Default HPR: Rch of Headphone-Amp Power Control 0: Normal Operation 1: OFF(Default) HPL: Lch of Headphone-Amp Power Control 0: Normal Operation 1: OFF(Default) BPMHP: BEEPM to Headphone-amp Enable...
Page 49 ASAHI KASEI [AK4537] Addr Register Name Mode Control 1 PLL1 PLL0 MCKO DIF1 DIF0 Default DIF1-0: Audio Interface Format Select (see Table 13) Default: “10” (ADC: I S, DAC: I BICK frequency Select at Master Mode 0: 64fs (Default) 1: 32fs This bit is invalid in slave mode.
Page 50 ASAHI KASEI [AK4537] Addr Register Name Mode Control 2 LOOP SPPS Default SPPS: Speaker-amp Power-Save-Mode 0: Power Save Mode (Default) 1: Normal Operation When the SPPS bit = “1”, the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-z and SPN pin is set to HVDD/2 voltage.
Page 51 ASAHI KASEI [AK4537] Addr Register Name DAC Control SMUTE DATTC BST1 BST0 DEM1 DEM0 Default DEM1-0: De-emphases response (see Table 16) Default: “01” (OFF) BST1-0: Select Low Frequency Boost Function (see Table 17) Default: “00” (OFF) DATTC: DAC Digital Attenuator Control Mode Select...
Page 52 ASAHI KASEI [AK4537] Addr Register Name MIC/HP Control IPGAC MPWRE MPWRI MICAD MSEL MGAIN Default MGAIN: 1 Mic-amp Gain control 0: 0dB 1: +20dB (Default) MSEL: Microphone select 0: Internal MIC (Default) 1: External MIC MICAD: Switch Control from Mic In to ADC...
Page 53 ASAHI KASEI [AK4537] Addr Register Name Timer Select ROTM ZTM1 ZTM0 WTM1 WTM0 LTM1 LTM0 Default LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = “1”) (see Table 25) The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by the period specified by the LTM1-0 bits.
Page 54 ASAHI KASEI [AK4537] Addr Register Name ALC Mode Control 1 ALC2 ALC1 ZELM LMAT1 LMAT0 RATT LMTH Default LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 28) The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about r2dB.
Page 55 ASAHI KASEI [AK4537] ALC1: ALC1 Enable Flag 0: ALC1 Disable (Default) 1: ALC1 Enable ALC1 is enabled when ALC1 bit is “1”. Default is “0”(Disable). ALC2: ALC2 Enable Flag 0: ALC2 Disable 1: ALC2 Enable (Default) ALC2 is enabled after initialization cycle(2048/fs=46.4ms@fs=44.1kHz). This initialization cycle starts when PMSPK bit is changed from “0”...
Page 56 ASAHI KASEI [AK4537] Addr Register Name Lch Input PGA Control IPGAL6 IPGAL5 IPGAL4 IPGAL3 IPGAL2 IPGAL1 IPGAL0 Rch Input PGA Control IPGAR6 IPGAR5 IPGAR4 IPGAR3 IPGAR2 IPGAR1 IPGAR0 Default IPGAL6-0: Lch Input Analog PGA (see Table 32) IPGAR6-0: Rch Input Analog PGA (see Table 32) Default: “10H”...
Page 57 ASAHI KASEI [AK4537] Addr Register Name Volume Control ATTM ATTS2 ATTS1 ATTS0 Default ATTS2-0: Attenuator select of signal from IPGA Lch to Stereo Mixer. (See Table 33) ATTS2-0 Attenuation -6dB 9dB 12dB Default 15dB 18dB 21dB 24dB -27dB Table 33. Attenuator Table ATTM: Attenuator control for signal from IPGA Lch to Mono Mixer 0: OFF.
Page 58 ASAHI KASEI [AK4537] Addr Register Name Power Management 3 PMIPGR PMMICR PMADR Default PMADR: ADC Rch Block Power Control 0: Power down (Default) 1: Power up When the PMADL or PMADR bit changes from “0” to “1”, the initialization cycle (2081/fs = 47.2ms @44.1kHz) starts.
Page 59 Reset DSP and uP Notes: - AVSS, DVSS, PVSS and HVSS of the AK4537 should be distributed separately from the ground of external controllers. - Values of R and C in Figure 47 should depend on system. - All input pins should not be left floating.
Page 60 Mic input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2SRC). The AK4537 can accept input voltages from AVSS to AVDD.
Page 61 (1) Power Supply (2) PDN pin = “L” o “H” “L” time of 150ns or more is needed to reset the AK4537. (3) Power up VCOM : PMVCM bit = “0” o “1” VCOM should first be powered up before the other block operates.
Page 62 ASAHI KASEI [AK4537] „ Clock Set up When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCLK, BICK and LRCK) must be supplied. 1. When X'tal is used in PLL mode. (Slave mode) MCKPD bit E x a m p le :...
Page 63 ASAHI KASEI [AK4537] 2. When X'tal is used in PLL mode. (Master mode) E x a m p le : MCKPD bit A u d io I/F F o r m a t : I (Addr:01H, D7) B IC K f re q u e nc y a t M a s te r M o d e : 6 4 f s I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z...
Page 64 ASAHI KASEI [AK4537] 3. When an external clock is used in PLL mode. (Slave mode) E xam p le : A u d io I/F F o r m a t : I MCKPD bit B IC K f re q u e nc y a t M a s te r M o d e : 6 4 f s (Addr:01H, D7) I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z...
Page 65 ASAHI KASEI [AK4537] 4. When an external clock is used in PLL mode. (Master mode) E xam ple : MCKPD bit A udio I/F Fo rm at : I (Addr:01H, D7) B IC K freq ue ncy at M a ste r M o de : 64fs Inp ut M aster C lo c k S e lect at P LL M o de : 1 1.2 896M H z...
Page 66 MIC block is powered-down. If the registers for the ALC1 operation are also changed when the sampling frequency is changed, it should be done after the AK4537 goes to the manual mode (ALC1 bit = “0”) or MIC block is powered-down (PMMICL bit = “0”). IPGA gain is reset when PMMICL =PMMICR=PMIPGL=PMIPGR= “0”, and then IPGA operation starts from the default value when...
Page 67 ASAHI KASEI [AK4537] „ Headphone-amp Output E x a m p le : X ’ta l a n d P L L a re u s e d . S a m p lin g F r e q u e n c y : 4 4 . 1 k H z D A T T C b it = “1 ”...
Page 68 ASAHI KASEI [AK4537] „ Speaker-amp Output FS2-0 bits (Addr:05H, D7-5) E x a m p le : X ’ta l a n d P L L a r e u s e d . ALC2 bit S a m p li n g F r e q u e n c y : 4 8 k H z D A T T C b it = “...
Page 69 ASAHI KASEI [AK4537] „ Stop of Clock MCLK can be stopped when PMMIC=PMADC=PMDAC=PMSPK= “0”. 1. When X’tal is used in PLL mode E x a m p le : MCKO bit A u d io I/F F o rm a t : I...
Page 70 „ Power down Power down VCOM(PMVCM= “1” o “0”) after all blocks except VCOM are powered down and MCLK stops. The AK4537 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized. MS0202-E-04...
Page 71 ASAHI KASEI [AK4537] PACKAGE 52pin QFN (Unit: mm) 0.20 + 0.10 7.2 ± 0.20 - 0.20 0.60 + 0.10 - 0.30 7.0 ± 0.10 4 - C0.6 45° 45° 0.40 0.18 ± 0.05 0.05 0.05 Note) The part of black at four corners on reverse side must not be soldered and must be open.
Page 72 ASAHI KASEI [AK4537] MARKING AK4537VN XXXXXXX XXXXXXX : Date code identifier (7 digits) MS0202-E-04 2005/04 - 72 - Downloaded from Elcodis.com electronic components distributor...
Page 73 ASAHI KASEI [AK4537] Revision History Date (YY/MM/DD) Revision Reason Page Contents 03/02/03 First Edition 03/03/24 Spec change: Headphone amp oscillation prevention circuit 0.22PF+10: o 0.22PFr20% capacitor and 10:r20% resistor Error correct: Pin/Function NC pin: “No internal bonding.” o “This pin should be left floating.”...
Page 74 ASAHI KASEI [AK4537] Date (YY/MM/DD) Revision Reason Page Contents 03/05/23 Explanation Manual Mode addition: “When writing IPGAL6-0 IPGAR6-0 bits continually, the control register should be written by an interval more than zero crossing timeout (the write operation interval between IPGAL6-0 and IPGAR6-0 bits also should be more than zero crossing timeout).
Page 75 ASAHI KASEI [AK4537] Date (YY/MM/DD) Revision Reason Page Contents 03/05/23 Explanation Register Definitions (IPGAL6-0 and IPGAR6-0 addition: bits) “When IPGA gain is changed, IPGAL6-0 and IPGAR6-0 bits should be written while PMMICL, PMMICR, PMIPGL or PMIPGR bit is “1” and ALC1 bit is “0”. IPGA gain is reset when PMMICL=PMMICR=PMIPGL =PMIPGR= “0”, and then IPGA operation...
Page 76 It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content...

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