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SDRAM PH Limit
This item specify the number of consecutive Page-Hit requests to
allow before choosing a non Page-Hit request. The settings are: 1/4/32/64
cycles.
SDRAM Idle Limit
This item specify the number of idel cycles to wait before precharging
an idle bank. The settings are: 1/8/32/64 cycles.
SDRAM Trc Timing Value
This item specify the minimum time to activate the same bank. The
settings are: 3/4/5/6/7/8 cycles or reserved.
SDRAM Trp Timing Value
This item specify the delay from precharge command to activate
command. The settings are 3/2/1 cycles
SDRAM Tras Timing Value
This item specify the minimum bank active time. The settings are: 2/
3/4/5/6/7 cycles or reserved.
SDRAM CAS latency
When synchronous DRAM is installed, the number of clock cycles
of CAS latency depends on the DRAM timing. The settings are: 2/3 cycles.
SDRAM Trcd Timing Value
This item specify the delay from activation of a bank to the time that a
read or write command is accepted. The settings are: 1/2/3/4 cycles.
3-14
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