Mipi; Figure 14 Blc Convergence Signal; Table 19 Mipi Control Register - Bg BG0836 Manual

BG0836 1/2.7 inch 1080P HD CMOS image sensor

MIPI

Name
MIPI_CTRL0
MIPI_CTRL1
MIPI_CTRL2
MIPI_CTRL3
MIPI_PCLK_
PERIOD
Raw10 and raw12 data output sequence is as shown in Figure 15 raw10/raw12 Data output sequence

Figure 14 BLC Convergence signal

BG0836 supports 1 lane MIPI output, it can reach 800Mbps.

Table 19 mipi control register

Address Width
16'h0390 7
16'h0391 8
16'h0392 7
16'h0393 4
16'h0398 8
Function
Bit[6:3]: Reserved
Bit[2]: MIPI clock continuous enable, clock Lane
output Continuously, valid high.
Bit[1]: MIPI module enable, mipi enable control，
valid high.
Bit[0]: Reserved
Bit[7:1]: Reserved
Bit[0]: Image data format control, 0-raw10, 1-
raw12
Bit[6:3]: Reserved
Bit[2]: Reserved
Bit[1]: Frame number enable in frame start(or
end)
1 - frame number enable(0~0xffff),
0 - frame number=0
Bit[0]: Reserved
Bit[3:1]: Reserved
Bit[0]: Data lane 0 HS enable，always 1。
Clock period used to calculate the mipi timing.
Set the value = 4 times to the mipi out clock
lane (directly discarded he decimal part)
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