Pll Control; Main System Clock Control; Figure 12 Pll Block Diagram; Table 10 Pll Control Register - Bg BG0836 Manual

BG0836 1/2.7 inch 1080P HD CMOS image sensor

PLL control

pre-divider
clkin
pln_p<5:0>
Register
PLM
PLN
PCLK_CTRL
When you adjust vco oscillation frequency, you need to set vco_freq_sel of PLLCTRL_P. Formula
for vco frequency is
Setting vco_freq_sel according to the following table.

Main System Clock control

clkin
pln_p+2
PFD
LPF
fvco
plm_p+2
loop-divider
plm_p<8:0>

Figure 12 PLL block diagram

The relationship between output
f
pixclk
Registers corresponding to PLL are listed in

Table 10 PLL control register

Addr
0x00f3
0x00f4
0x00f5
0x006d
Table 11 PLL VCO
vco_freq_sel<1:0>
00 B
01 B
10 B
11 B
Mclk（Main System Clock）can be chosen as Clkin (external clock ) or the frequency
multiplication of Pclk(Pixel output clock).
CP
VCO
vco_fsel_p<1:0>
fvco
Pclk frequency and clkin frequency
( plm + 2 ) ∗ f
clkin
=
( pln + 2 ) ∗ (pclkdiv + 2)
Width
9 PLM data
6 PLN data
Bit[6] Reserved
7 Bit[5:4] vco_freq_sel
Bit[2:0] pclkdiv
�� = �� ∗ (������_�� + 2) (������_�� + 2)
vco ����������
frequency setting up corresponding table
vco frequency range
200M ~ 380M
230M ~ 460M
360M ~ 600M
500M ~ 770M
16/ 24
fpll=fvco
pclk_sel
pllclk_sel
pclkdiv<2:0>
Table 10:
Function
⁄
V1.2
fpll
pclkdiv+2
pixclk
is :