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CLD- D925
Ol
SSS
netion —OSOSOSCSCSCCCCC'C;C™~*r
IVDD——s|_- — _| To be connected to +5 V (VDD for the AD converter)
IVRL
st
Provides the AD converter with the reference voltage for the L side
XPBCSY
Lt | The PB composite sync is to be supplied here with negative logic
lvSS_—_—|_— _| To be connected to GND (VSS associated with the logic)
| ot | Accepts an RF signal for the spindle servo
TBCCK/512
Outputs a 1/51 2th division (approx. 28 kHz) of the clock (NTSC: 4 fsc, PAL: 4 fp) used for TBC
It is used to generate a chopping wave for spindle control.
jposp
Accepts the dropout detection pulse. The pulse will be internally stretched.
Flag output to indicate the positions for level clamp of the pilot-burst signal in PAL.
47
Output pin for a phase-frequency error of the spindle errors. It outputs the result of comparison between PBH and
reference H in tristate. The polarity can be set by a command (PERPOL).
The stretch volume is set by a command (STDO-3)
PBCLP
ie (See the exampie of input specifications.)
GCONT
ACCONT
PPXO
PPX!
D
Outputs a PWM signal according to the command-specified value (CD0-3)
Tristate output of the acceleration/deceleration signal, which depends either on the forced acceleration/deceleration
signal, the error detection by RF or error detection by H sync. The acceleration/deceleration volume is determined
by setting the duty of the PWM output by commands (RFGDO-3, HFGDO-3).
The polarity can be set by a command (ACCPOL).
loop filter and the chopping wave externally generated from TBCCK/512.
Accepts a signal obtained through the voltage comparison between the spindle error which has passed through a
loop filter and the destination voltage.
Control signal output for Tr which drives the spindle motor. It is applicable to either a brush motor or brushless
DRVB
motor, selection of which is by a command (BLM). (See the functional block diagram for the logic.)
7
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Po
Foe
foco2z | 0 | Outputs a signal obtained through waveformshaping ofthe DCOT signal
pcos | 0 | Outputs a signal obtained through waveformshaping ofthe DCO3signal SCS
TO [Outputs a signalmulipiedby2
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Outputs a signal multiplied by 2
[vss
[vss
72 | DCOO
To be connected to +5 V (VDD for input multiplied by 4)
It can be fixed to the minimum potential by a command (DCOINH)
VREF
Input to show the reference voltage to the internal power source for the DA converter
78/VDD
—_—_—i|_— _[ To be connected to +5 V (VDD for the internal power source for the DA converter)
l77jres
| 10 | Pin to specify the intemal current of the internal power source for the DA converter
Connect 5.1 kohms as standard between this pin and GND.
l7a{vbD
|
— | To be connected to +5 V (VDD for the DA converter for VOUT output)
VOUT
| 0 | Time-base-corrected video output. While a composite sync is normally inserted, the sync position will be found at
To be connected to +5 V (VDD for output multiplied by 4)
To be connected to GND (VSS for output multiplied by 4)
Write clock input for PAL. Accepts the DCO7 output via a 4-fp filter.
°o
< "n n
| ~lN
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o = N/a
< n n
the pedestal level in memory system mode. (However, some half-H pulses etc. may partly remain near V sync.)
fso{vss
|
= | To be connected to GND (VSS for the DA converter for VOUT output)
77
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