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THEORY OF OPERATION
5.5 CONTROL
CIRCUITRY
The signals
for the circuitry
that provides
control
of the
various
FETs, relays and logic levels are supplied
by the
shift
store
registers
UI37,
Ul38,
LJ13Y, U140 and
UlO3
(Model
7931). CLOCK,
DATA and STROBE signals are sent
from the VIA (U310) acruss the pulse transformers
'1302,
I303 and l304. The pulse transformers
provide
500V isola-
tion between
the analog and digital
sections
of the instru-
ment.
DATA is serially
loaded
into the shift store registers
and a STROBE pulse causes the registers to simultaneously
output
the appropriate
logic levels to the FE'1 and relay
drivers.
During
high speed mcasuremcnts
(500 readings
to the buffer),
registers
U138, U13Y and U14O are not used
5.6 DIGITAL
CIRCUITRY
The Model lY3 is controlled
by an internal
microcomputer.
This
section
briefly
describes
the
operation
of
the
microcomputer
and associated
digital
circuitry.
Refer to
schematic
diagram
number
~193.106 for circuit
details.
5.6.1 Microcomputer
The
microcomputer
ccntcrs
around
the
X-bit
h8BO9
microprocessor.
The
MI'U
has direct
control
over
the
display,
front panel switches,
A/D converter,
IEEE-488 bus,
as well as the VOIdTMETER
COMPLETE
Output
and the
EXrEIZNAL
TRIGGER
Input.
Timing
for
the
micre
processor
is accmn
lished
by the use of Y301; an BMHz
crystal.
Internally,
t R. 1s frequency
is divided
down
by four
to obtain
a bus operating
frequency
of 2MHz.
Instrument
operation
software
is stored in EPROMs
U314
and U31.5. The revision
Icvel of this software
is displayed
on power-up.
Calibration
constan&
and instrument
set-up
conditions
are stored in E2PROM
(U312). U313 is the RAM
and has battery
back-up.
Partial address
decoding
is used
in this system.
The function
selected is determined
by the
state of All,
A12, A13, Al4 and Al5 address
lines. These
address
lines determine
which
is sclcctcd
by the decoders.
The decoders
are U303, U307 and U304. Only
~,ne device
(ROM,
RAM,
VIA,
etc) will
have access to the data bus
at any one tmle.
The battery
(or capacitor)
back-up
circuitry
turns on when
power is turned
off. The battery
(or capacitor)
is connected
to the RAM
circuitry.
This retains
the data in the buffer
locations
when
the power
is shut down.
When
power
is
lost, transistors
Q301 and Q3O2 turn
off and the battery
(or capacitor)
voltage
is routed
through
I~309 to the RAM
circuitry.
The heart of the IEEE-488
circuitry
is the GI'IBA
(U?lh).
The GI'IBA
is capable of performing
all IEEE talker-listener
protocols.
The bidirectional
data lines DO through
117 prr-
mit the transfer
of data bctwccn
the microprocessor
and
the CI'IBA.
The transceivers
U308 and UXl7 are used to
drive the output.
Dale is buffewd
by U308 and Ll317 and
is transmilled
to the bus via connector
JlO~l3.
5.6.2
Display
Circuitry
The display
information
is sent through
display
latches
U309 and U318. Upon
each display
update,
new segment
information
is prcscnted
to the display
latches and a clock
pulse is sent on I'AO. The clock pulse to U403 shifts a digit
enable
bit to the next digit
to be enabled.
Every
~14 times
the display
is updated,
a digit
enable
bit is generated
at
PA7 and goes to the data input
of the shift register.
U406
through
U409 are the drivers
for the LED segments
of the
display
digits
and the LED indicators.
5.7 POWER SUPPLIES
'The main power
supplies
of the Model
793 are located on
sheet 2 of 2 of schematic
drawing
number
193.106. Fuse
F301 is the line fuse which
is accessible
from the rear panel.
5301 is the POWER
ON/OFF
switch
and 5302 selects 115V
or 230V operation
by placing
the transformer
primary
will-
dings in parallel
or series. The power
transformers,
'1301,
has three
secondary
windings;
one for the +5V digital
supply,
one for the +5V analog
supply
and one for the
+15V analog
supply.
CR302, CR303 and CR304 provides
fullwave
rectification
for the three supplies,
while
U301,
VR301, VR302 and VR303 provides
the regulation.
5-10
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