Ic Block Diagrams - Sony CMT-CP300 Service Manual

6-21. IC BLOCK DIAGRAMS

IC101, 201 TDA7296 (MAIN BOARD)
BIPOLAR
TRANSCONDACTANCE
INPUT STAGE
MOS GAIN &
–
LEVEL SHIFTING
+
BOOST-
1 2 3 4 5
µPD7225G (MAIN BOARD)
IC602
3
V 1
LC
LCD
V 2 4
LC
TIMING
V 3 5
LC CONTROL
2
SYNC
52
CL1 SEGMENT
OSC
DECODER
CL2 1
V
DD
V
6
SS
13
RESET
V
6
SS
WRITE CONTROL
13
RESET
13
RESET
IC603 BU1924AF (MAIN BOARD)
16 15 14 13
CLOCK
DEFFERENTIAL
DECODER
1 2 3 4
THERMAL
SHUTDOWN
MOS SHORT
OUTPUT CIRCUIT
STAGE
STAGE PROTECTION
STANDBY/
MUTE
STRAP
6 7 8 9 10 11 12
S0 – S13 , S14 – S31
19 – 32 , 34 – 51
LCD DRIVER
DESPLAY DATA LATCH
DATA DATA
MEMORY POINTER
COMMAND / DATA REGISTER
SIRIAL INTERFACE
9 8
12 11 10
TEST
BIPHASE PLL PLL 57KHz
DECODER 1187.5Hz RDS/ARI
8TH SWITCHED
CAPACITOR
FILTER
5 6 7
13 14 15
18 17 16 15
BLINKING
DATA
MEMORY
COMMAND
DECODER
9
8
HCD-CP300
37