Table of Contents
Advertisement
TO:
Q The
Q
Counter
R The Receive Data Lines
S The Insert Switches
A The A Register
B The B Register
C The C Counter
T The Transmit Data Lines
If
R, S, or Tare specified, the Control Bit 1, Control Bit 2, and Parity Flip-Flops (Internal Func-
tions} are used for the "extra" positions, since R and Tare all more than 18 bits.
If
R is specified in the FROM group, after the data is transferred, the Receive Flag and Receive
Buffer are reset by an automatically generated signal activating External Function Driver Number
1 (EFDl}.
If
T is specified in the TO group, before the data is transferred, the Transmit Flag and Transmit
Buffer are reset by an automatically generated signal activating External Function Driver Number
2 (EFD2).
When a register transfer instruction is executed, the contents of those registers which are speci-
fied to be used as the FROM group for this instruction are logically "OR-ed" together into the
Y
Register.
Then the data goes from Y to Z with the operation specified by the instruction being
performed on the data as it goes from
Y
to Z. Finally the result goes from the Z drivers to all
of those registers which are specified in the TO group. The Plus, Zero, and Even Flip-Flops will
take on their new states in the normal manner.
If
no registers are specified in the FROM group,
the output from the
Y
Register will be zero.
If
no registers are specified in the TO group, the
only outputs are the new states of the Plus, Zero, and Even Flip-Flops. As an example, the
instruction TRA AQ, BT can be represented by the equations B=T=(A OR Q).
MNEMONIC
OPERAND
TRA
FROM, TO
TRC
FROM, TO
SLl
FROM, TO
SRl
FROM, TO
SL6
FROM, TO
WORD TIMES
1
1
1
1
1
DESCRIPTION
TRANSFER. In going from
Y
to A, no change
is made in the data.
TRANSFER COMPLEMENT. In going from
Y to Z, the data is changed into its ones
complement.
SHIFT LEFT ONE.
In going from Y to Z,
the data is shifted left one position.
The
high-order bit is lost and a zero goes into
the low-order position.
SHIFT RIGHT ONE.
In going from
Y
to Z,
the data is shifted right one position.
The
low-order bit is lost and a zero goes into
the high-order position.
SHIFT LEFT SIX.
In going from Y to Z,
the data is shifted left six positions. The six
high-order bits are lost and zeros go into the
six low-order positions.
@&IY&~~IJc:J ~®------------
-75-
Advertisement
Table of Contents
