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A.1 Watchdog Timer Programming
AEC-6613 utilizes the ITE 8783 chipset as its watchdog timer controller. Below are the
procedures to complete its configuration and the AAEON initial watchdog timer
program is also attached based on which you can develop customized program to fit
your application.
Configuring Sequence Description
After the hardware reset or power-on reset, the ITE 8783 enters the normal mode
with all logical devices disabled except KBC. The initial state (enable bit ) of
this logical device (KBC) is determined by the state of pin 121 (DTR1#) at the falling
edge of the system reset during power-on reset.
There are three steps to complete the configuration setup: (1) Enter the MB PnP Mode;
(2) Modify the data of configuration registers; (3) Exit the MB PnP Mode. Undesired
result may occur if the MB PnP Mode is not exited normally.
(1) Enter the MB PnP Mode
To enter the MB PnP Mode, four special I/O write operations are to be performed
during Wait for Key state. To ensure the initial state of
Appendix A – Watchdog Timer Programming
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