Table of Contents Revision History ....................1 Introduction......................1 1. Specifications......................2 2. Overview........................ 3 2.1. Name of Parts ....................3 2.2. Block Diagram ....................4 2.3. Power Supply ..................... 4 2.4. JTAG Connector....................5 3. Configuration Switch..................... 6 4. FPGA Configuration ....................7 5.
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HuMANDATA will revise the diagram. When a problem can be solved only by replacing components or modifying the product, HuMANDATA will take back the product to replace it with a properly functioning product.
Revision History Revision Date Description v1.0 Jul. 15, 2009 Initial release Correct a FPGA name in Section 1 v1.1 Nov. 12, 2009 Updata a block daiagram in Section 2.2 Introduction Thank you for buying our product XCM-303-50AN. This is an evaluation board equipped with a Xilinx FPGA Spartan-3AN, power, reset, and clock circuit.
1. Specifications Model Name XCM-303-50AN FPGA XC3S50AN- 4TQG144C User I/Os User Switch User LEDs On-Board Clock 50 [MHz] (External inputs are available) Status LEDs 3 (POWER, DONE, AWAKE) Power-On Reset 240 [ms] typ. (Configuration Reset Signal) JTAG Connector SIL 7-pin socket, 2.54 [mm] pitch DC 3.3 [V] Power Input (Internal power is generated by an on-board regulator.)
2. Overview 2.1. Name of Parts User I/Os (CNB) User Switch User LEDs Oscillator 50 MHz JTAG Power & POR FPGA Config. Switch Status LEDs User I/Os (CNA) Component side XCM-303-50AN v1.1...
2.2. Block Diagram VIO(B) INPUT External CLK User I/Os CNB Oscillator JTAG JTAG Buffer PROG_B Power-On Reset Typ. 240ms DONE LED Spartan-3AN XC3S50AN AWAKE LED Power Circuit -4TQG144C 1.2V User LED Config. Switch Power LED (3.3V) User Switch User I/Os CNA 3.3 V INPUT External CLK 2.3.
2.4. JTAG Connector This connector is used to configure the FPGA and program the configuration device in-system. Pin assignment is as follows. Signal Name Direction JTAG Pin VCC(3.3V) OUT(POW) You can use Xilinx download cable. Notice Please pay attention not to attach cables in reverse. XCM-303-50AN v1.1...
3. Configuration Switch The specification of configuration switch is below. “ON” means “Low (Ground)”. Position No. Net Label PSW1 X_M0 X_M1 X_M2 X_SUSPEND Default Function Mode Select Pin SPI Configuration Mode Suspend Mode User SW Internal Master SPI Master Serial Master SPI Master BPIUP JTAG...
4. FPGA Configuration To configure the FPGA via JTAG, please refer to the following steps. 1. Double-click [Configuration Target Device] in [Processes] tab. 2. Select [Configure devices using Boundary-Scan (JTAG)]. 3. Open the bit file you made. 4. Confirm [Verify] is not checked in [Device Programming Properties] dialog. 5.
6. Additional Documentation and User Support The following documents and other supports are available at http://www.hdl.co.jp/en/spc/XCM/xcm-303/ Circuit Schematic Pin List Dimensional drawing PCB drawing Net List … and more. XCM-303-50AN v1.1...
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