1. Manuals
  2. Brands
  3. THine Manuals
  4. Transmitter
  5. SerDes THCV231-Q
  6. Manual

THine SerDes THCV231-Q Manual

Transmitter and receiver with bi-directional transceiver
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
THCV231-Q_THCV236-Q_Rev.2.60_E
THCV231-Q and THCV236-Q
General Description
The THCV231-Q and THCV236-Q are designed to
support video data transmission between the host and
display.
THCV231-Q
One high-speed lane can carry up to 14bits data at a
pixel clock frequency from 12MHz to 160MHz.
THCV236-Q
One high-speed lane can carry up to 32bit data and
3bits of synchronizing signals at a pixel clock
frequency from 6MHz to 160MHz by converting
RGB444 to YCbCr422.
The chipset, which has one high-speed data lane,
can transmit video data up to 1080p/60Hz.
The maximum serial data rate is 4.00Gbps/lane.

Block Diagram

THCV231-Q
D11-D0
HSYNC
VSYNC
CLKIN
Settings
2-wire I/F
SDA/SCL
Copyright©2017 THine Electronics, Inc.
SerDes transmitter and receiver with bi-directional transceiver
TXP
TXN
TCMP
TCMN
Controls
OSC
CAPOUT
LDO
CAPINA
CAPINP

Features

Data width selectable
Wide frequency range
AC coupling for high-speed lanes
CDR requires no external frequency reference
Wide range supply voltage from 1.7V to 3.6V
Additional spread spectrum on data stream
2-wire serial interface bridge function(400kbps)
Remote side GPIO control and monitoring
THCV231-Q
QFN32 (5mm x 5mm) with exposed pad ground
THCV236-Q
QFN64 (9mm x 9mm) with exposed pad ground
AEC-Q100 Grade 2 (-40 to 105degC)
ISO/TS16949 compliant
EU RoHS compliant
THCV236-Q
RXP
RXN
RCMP
RCMN
Controls
OSC
1/58
D31-D0
HSYNC
VSYNC
DE
CLKOUT
Settings
2-wire I/F
SDA/SCL
LDO
CAPOUT
CAPINA
THine Electronics, Inc.
Security E

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SerDes THCV231-Q and is the answer not in the manual?

Questions and answers

Related Manuals for THine SerDes THCV231-Q

Summary of Contents for THine SerDes THCV231-Q

  • Page 1: Contents Page General Description

    Block Diagram THCV231-Q THCV236-Q D11-D0 D31-D0 HSYNC HSYNC VSYNC VSYNC CLKIN CLKOUT TCMP RCMP Settings Settings TCMN RCMN Controls Controls 2-wire I/F 2-wire I/F SDA/SCL SDA/SCL CAPOUT CAPOUT CAPINA CAPINA CAPINP Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 1/58 Security E...

  • Page 2: Table Of Contents

    Absolute Maximum Ratings ..........................40 Recommended Operating Conditions ........................ 40 Electrical Specification ............................40 LVCMOS DC Specification ..........................40 CML DC Specification ............................41 CML Bi-Directional DC Specification ......................41 Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 2/58 Security E...
  • Page 3 2-wire serial I/F Switching Characteristics ....................... 51 GPIO Switching Characteristics ........................53 PCB Layout Guideline regarding VDD and AVDD for THCV236-Q ............. 55 Package ................................. 56 Notices and Requests ............................58 Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 3/58 Security E...

  • Page 4: Pin Configuration

    (QFN 32pin) HSYNC CAPOUT (TOP VIEW) TCMP TCMN CLKIN 33 EXPGND CAPINA CAPINP THCV236-Q (QFN 64pin) HSYNC HTPDN/SUBMODE CLKOUT LOCKN/MSSEL (TOP VIEW) CAPOUT 65 EXPGND CAPINA MAINMODE/RCMN HFSEL/RCMP D24/GPIO3 RXDEFSEL D25/GPIO4 Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 4/58 Security E...

  • Page 5: Pin Description

    CO : CML Output buffer , CB : CML Bi-directional buffer I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , B : LVCMOS Bi-directional buffer PWR : Power supply , GND : Ground Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 5/58...

  • Page 6: Pin Description For Thcv236-Q

    When GPIO0 is used as Open-Drain Output, it must be connected with a pull-up resistor to VDD. When GPIO0 is used as push pull output or input, no external component is required. Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 6/58 Security E...
  • Page 7 When GPIO2 is used as Open-Drain Output, it must be connected with a pull-up resistor to VDD. When GPIO2 is used as push pull output or input, no external component is required. CLKOUT Clock Output D31-D26 12-15,17,18 Pixel Data Output Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 7/58 Security E...
  • Page 8 I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer PWR : Power supply , GND : Ground Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 8/58...
  • Page 9 *1 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output. *2 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input. *3 Through GPIO input is default on register setting Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 9/58...

  • Page 10: Functional Overview

    CAPOUT, CAPINA and CAPINP must be tied together. Power supply AVDD is supposed to be stabilized with de-coupling capacitor and series noise filter (for example, ferrite bead). Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 10/58 Security E...

  • Page 11: Power Down (Pdn1, Pdn0, Pdn)

    This function is controlled by OUTSEL pin or OUTSEL_ENABLE register and OUTSEL_SETTING register. See Table 5. Table 5. Permanent Clock Output function table (PDN1=1) OUTSEL_ OUTSEL_ Output Clock ENABLE SETTING Frequency (*1) (register) (register) 80MHz 40MHz(default) 20MHz 10MHz *1 typical value Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 11/58 Security E...

  • Page 12: Spread Spectrum Clock Generator (Sscg)

    HFSEL and LFSEL settings, input clock frequency and FMOD register setting (default value 0xD). Refer to following formula.  CLKSSCG  FMOD is the frequency listed in Table 9 and Table 10. CLKSSCG Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 12/58 Security E...
  • Page 13 Forbidden Setting Up to 0.5 % spread at the 30kHz modulation frequency is stable for most cases. In case of using out of this range, please verify at the actual system. Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 13/58 Security E...

  • Page 14: Data Enable

    HS Mode (MAINMODE=0) and High Frequency Mode (HFSEL=1), the period between rising edges of DE (tDEINT), high time of DE (tDEH) should always satisfy following equations. tDEH = tTCIP*(2m) and tDEINT = tTCIP*(2n), m,n=2,3,4,5,6…… Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 14/58...

  • Page 15: Hot-Plug Function

    CDR lock is done. Then the CDR training mode finishes and the Transmitter shifts to the normal operation. LOCKN is transferred via Sub-Link line. HOST MPU can confirm LOCKN state by reading Sub-Link Master register (0x00 bit1 LOCKN). Figure 4. HTPDN, LOCKN transmission route Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 15/58 Security E...

  • Page 16: Field Bet Operation

    *1 THCV231-Q: Register setting (0x53 bit1), THCV236-Q: Pin setting *2 Register setting (0x53 bit0, Default 0) Table 13. THCV236-Q Main-Link Field BET Result BETOUT Output Bit Error Occurred No Error Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 16/58 Security E...
  • Page 17 THCV231-Q THCV236-Q Test Pattern Test Pattern RF/BETOUT Sub-Link Generator Checker Test Point Field BET BET=1 BET_SEL=1 BET=1 BET_SEL=1 LATEN/SD3/AIN1/GPIO0 =1 (Register) (Register) (Pin) (Register) Figure 6. Sub-Link Field BET Configuration Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 17/58 Security E...

  • Page 18: Data Width And Frequency Range Select Function

    *2 V-by-One®HS mode operation requires Data Enable (DE) signal rule. Please refer to the related section. *3 HSYNC signal can be assigned to Data Enable input when V-by-One® HS mode requirements are met. Copyright©2017 THine Electronics, Inc. THine Electronics, Inc.

  • Page 19: 2-Wire Serial I/F Mode

    When 2WIRE_MODE = 01, Sub-Link Master device informs HOST MPU that Sub-Link Slave register access or remote side 2-wire serial register access has been completed by interruption (INT pin) without clock stretching. Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 19/58...
  • Page 20 THCV231-Q_THCV236-Q_Rev.2.60_E Figure 7. 2WIRE_MODE Operation Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 20/58 Security E...

  • Page 21: Read/Write Access To Sub-Link Master Register

    Figure 8. Host to Sub-Link Master Register access configuration Figure 9. 2-wire serial I/F write to Sub-Link Master register protocol Figure 10. 2-wire serial I/F read to Sub-Link Master register protocol Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 21/58 Security E...

  • Page 22: Read/Write Access To Sub-Link Slave Register

    *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 22/58 Security E...
  • Page 23 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 23/58 Security E...

  • Page 24: Read/Write Access To Remote Side 2-Wire Serial Slave Devices Connected To Sub-Link Slave Device

    *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 24/58 Security E...
  • Page 25 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 25/58 Security E...
  • Page 26 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 26/58 Security E...
  • Page 27 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 27/58 Security E...

  • Page 28: Gpio

    GPIOn_INPUT_MONITOR (n=4,3) ). Each GPIO output signal goes to Low when Sub-Link communication fails. Sub-Link communication status can be observed by register read (0x82 bit2 COMERR_INT). *1 See Table 28 Figure 13. Through GPIO Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 28/58 Security E...
  • Page 29 GPIO IO Direction Number (I:Input, O:Output, -:Unavailable) Master/Slave Address Value Address Value Input Output GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 (HEX) (BIN) (HEX) (BIN) XXX11XXX XXX10XXX Master 0x40 XXX00XXX 0x43 XXX00XXX Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 29/58 Security E...

  • Page 30: Interruption

    Table 32(Address 0x02, 0x03) and Table 33(Address 0x82, 0x83). Figure 15. 2-wire serial I/F Interrupt to HOST access configuration Table 31. Interrupt output State Interrupt occurred Steady state Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 30/58 Security E...

  • Page 31: Register Map

    Sub-Link Slave (2-wire serial master) is connected to external 2-wire serial slave devices. Sub-Link Master device has address 0x00-0x7F, Sub-Link Slave device has address 0x80-0xFF. See Figure 16. Figure 16. Sub-Link Master/Slave device Register Address configuration Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 31/58...
  • Page 32 1: "SLINK_TIMEOUT_INT" is allowed to take action on INT output These registers are always active independent of Interrupt permission register. When No clock stretching mode, the value is 1 fixed, otherwise 0 fixed Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 32/58...
  • Page 33 Reserved 0x2C RD_START_16B 2-wire serial I/F Read Access Start Trigger for 16bit Register Address device 0x00 Reserved 0x2D-0x3F Assignment of 2-wire serial slave device address connected to Sub-Link Slave outside Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 33/58 Security E...
  • Page 34 Reserved. Must be 0 0x00 Reserved 0x8F Reserved 0x90 0x00 Reserved -0xBF Interrupt signal from Sub-Link Slave is reported to Sub-Link Master as Cause of interrupt Sub-Link Slave Side (0x02 bit4 SLAVESIDE_INT). Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 34/58 Security E...
  • Page 35 Active only when GPIO type is set as "Programmable GPIO" and set as output port. Filter eliminates input glitch shorter than t GPIO input transition is counted as GPIO_INT(0x82 bit3). Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 35/58 Security E...
  • Page 36 Reserved. Must be default setting. 0xFC Reserved 0xXX PLL_SET2 SSCG PLL setting (*3) 0xFD-0xFF 0xXX Reserved. Must be default setting. See Table 4 SSEN=1 and SPREAD=0 setting is forbidden See Table 8, Table 17 Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 36/58 Security E...
  • Page 37 Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0 , RXDEFSEL=0 → default value is 1. Filter eliminates input glitch shorter than t GPIO input transition is counted as GPIO_INT(0x02 bit3). Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 37/58...
  • Page 38 0: GPIO1 is open-drain output 1: GPIO1 is push pull output GPIO0 output buffer select GPIO0_OUTBUF_SEL 0: GPIO0 is open-drain output 1: GPIO0 is push pull output 0x47 0x00 Reserved -0x4F Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 38/58 Security E...
  • Page 39 SSEN=1 and SPREAD=0 setting is forbidden Described value is typical value. It has variation in the range from min spec value to max spec value of t See Table 8, Table 17 Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 39/58...

  • Page 40: Absolute Maximum Ratings

    Input Leak Current High I,IL VIN=VDD Input Leak Current Low I,IL VIN=0V Output Leak Current High IOZH O,B,BO VIN=VDD in Hi-Z State Output Leak Current Low in IOZL O,B,BO VIN=0V Hi-Z State Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 40/58 Security E...

  • Page 41: Cml Dc Specification

    Ω Bi-Directional Buffer RTERM Termination Resistance Receiver State Ω Bi-Directional Buffer VBOD RDIFF=400Ω Differential Output Voltage Bi-Directional Buffer VDD- VBOC Common Output Voltage Bi-Directional Buffer TRI-STATE IBOZ PDN=0(THCV231-Q) Current PDN1=0(THCV236-Q) Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 41/58 Security E...

  • Page 42: Supply Current

    PDN Low to CML Output High tTPLL1 Fix Delay LOCKN High to Training tTNP0 Pattern Output Delay LOCKN Low to Data Pattern tTNP1 Output Delay *1 MAINMODE and HFSEL are registers. Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 42/58 Security E...
  • Page 43 Bi-Directional Buffer Unit Interval Bi-Directional Buffer tBRF 1000 Rise and Fall Time(20%-80%) Bi-Directional Buffer tBPJTX Transmitter Period Jitter Accuracy (peak to peak) Bi-Directional Buffer tBPJRX Receiver Period Jitter Tolerance (peak to peak) Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 43/58 Security E...
  • Page 44 Setup time for STOP condition 386×t SU;STO Bus free time between a STOP and START condition *1 Please adjust Pull-up resistor and bus capacitance to meet the spec value. Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 44/58 Security E...
  • Page 45 Sub-Link Master interrupt valid Sub-Link Master interrupt reset delay Sub-Link Slave interrupt valid 2WIRE_MODE=00 Sub-Link Slave interrupt reset delay 2WIRE_MODE=01 Programmable GPIO input data setup 10000×(1/f Programmable GPIO input data hold Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 45/58 Security E...

  • Page 46: Ac Timing Diagrams And Test Circuits

    THCV231-Q_THCV236-Q_Rev.2.60_E AC Timing Diagrams and Test Circuits LVCMOS Input, Output Switching Characteristics Figure 17. LVCMOS Input Switching Timing Diagrams Figure 18. LVCMOS Output Switching Timing Diagrams Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 46/58 Security E...

  • Page 47: Cml Output Switching Characteristics

    THCV231-Q_THCV236-Q_Rev.2.60_E CML Output Switching Characteristics Figure 19. CML Output Switching Characteristics Figure 20. CML Buffer Equivalent Circuit Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 47/58 Security E...

  • Page 48: Cml Bi-Directional Output Test Circuit

    THCV231-Q_THCV236-Q_Rev.2.60_E CML Bi-directional Output Test Circuit Figure 21. Bi-directional CML VBOD/VBOC Test Circuit Figure 22. Bi-directional CML Switching Timing Diagram and Test Circuit Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 48/58 Security E...

  • Page 49: Latency Characteristics

    THCV231-Q_THCV236-Q_Rev.2.60_E Latency Characteristics Figure 23. THCV231-Q Latency Figure 24. THCV236-Q Latency Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 49/58 Security E...

  • Page 50: Lock And Unlock Sequence

    THCV231-Q_THCV236-Q_Rev.2.60_E Lock and Unlock Sequence Figure 25. THCV231-Q Lock/Unlock Sequence Figure 26. THCV236-Q Lock/Unlock Sequence Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 50/58 Security E...

  • Page 51: 2-Wire Serial I/F Switching Characteristics

    2-wire serial I/F Switching Characteristics Figure 27. 2-wire serial interface Timing Diagram Figure 28. Write access completion time to Sub-Link Slave register Figure 29. Read access completion time to Sub-Link Slave register Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 51/58 Security E...
  • Page 52 THCV231-Q_THCV236-Q_Rev.2.60_E Figure 30. Write access completion time to Remote side 2-wire serial slave register Figure 31. Read access completion time to Remote side 2-wire serial slave register Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 52/58 Security E...

  • Page 53: Gpio Switching Characteristics

    Figure 33. Programmable GPIO input timing at Sub-Link Master side Figure 34. Programmable GPIO output timing at Sub-Link Master side Figure 35. Programmable GPIO output timing at Sub-Link Slave side Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 53/58 Security E...
  • Page 54 Data_A (Sub-Link Slave side) Internal Interrupt Event (Sub-Link Slave side) INT of Sub-Link Master Figure 38. GPIO input and other interrupt event timing at Sub-Link Slave side (No-Clock Stretching Mode) Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 54/58 Security E...

  • Page 55: Pcb Layout Guideline Regarding Vdd And Avdd For Thcv236-Q

    AVDD and VDD, and separate the distance as possible (Example). Don’t set through-holes next to each other between ferrite beads and AVDD/VDD pins (Bad Example). Good Example 1 Good Example 2 Example Bad Example Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 55/58 Security E...

  • Page 56: Package

    THCV231-Q_THCV236-Q_Rev.2.60_E Package Unit : mm Figure 39. 32-pin QFN package physical dimension Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 56/58 Security E...
  • Page 57 THCV231-Q_THCV236-Q_Rev.2.60_E Unit : mm Figure 40. 64-pin QFN package physical dimension Copyright©2017 THine Electronics, Inc. THine Electronics, Inc. 57/58 Security E...

  • Page 58: Notices And Requests

    Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user’s request, testing of all functions and performance of the product is not necessarily performed.

This manual is also suitable for:

Serdes thcv236-q

Table of Contents