THine CEL SerDes THCV235-Q Manual

Transmitter and receiver with bi-directional transceiver

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General Description
The THCV235-Q and THCV236-Q are designed to
support video data transmission between the host and
display.
One high-speed lane can carry up to 32bit data and
3bits of synchronizing signals at a pixel clock
frequency from 6MHz to 160MHz by converting
RGB444 to YCbCr422.
The chipset, which has one high-speed data lane,
can transmit video data up to 1080p/60Hz.
The maximum serial data rate is 4.00Gbps/lane.

Block Diagram

THCV235-Q
D31-D0
HSYNC
VSYNC
DE
CLKIN
Settings
2-wire I/F
SDA/SCL
THCV235-Q_THCV236-Q_Rev.3.40_E
Copyright©2016 THine Electronics, Inc.
THCV235-Q and THCV236-Q
SerDes transmitter and receiver with bi-directional transceiver
TXP
TXN
TCMP
TCMN
Controls
OSC
CAPOUT
LDO
CAPINA
CAPINP

Features

Color depth selectable:24/32bit
RGB  YCbCr422 color space conversion
function
Wide frequency range
AC coupling for high-speed lanes
CDR requires no external frequency reference
Wide range supply voltage from 1.7V to 3.6V
Additional spread spectrum on data stream
2-wire serial interface bridge function(400kbps)
Remote side GPIO control and monitoring
Low speed data bridge function
QFN64(9mm x 9mm) with exposed pad ground
Automotive grade product : AEC-Q100 Grade 2
compliant
ISO/TS16949 compliant
®
V-by-One
HS standard version1.4 compliant
EU RoHS compliant
THCV236-Q
RXP
RXN
RCMP
RCMN
Controls
OSC
1/68
D31-D0
HSYNC
VSYNC
DE
CLKOUT
Settings
2-wire I/F
SDA/SCL
CAPOUT
LDO
CAPINA
THine Electronics, Inc.
Security E

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Table of Contents
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Summary of Contents for THine CEL SerDes THCV235-Q

  • Page 1: Contents Page General Description

    THCV235-Q THCV236-Q D31-D0 D31-D0 HSYNC HSYNC VSYNC VSYNC CLKIN CLKOUT TCMP RCMP Settings Settings TCMN RCMN Controls Controls 2-wire I/F 2-wire I/F SDA/SCL SDA/SCL CAPOUT CAPOUT CAPINA CAPINA CAPINP THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 1/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 2: Table Of Contents

    Read/Write access to remote side 2-wire serial slave devices connected to Sub-Link Slave Device .... 31 GPIO ................................35 Interruption ..............................38 Low Speed Data Bridge Mode ........................39 Register Map ................................ 40 Absolute Maximum Ratings ..........................50 Recommended Operating Conditions ........................ 50 THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 2/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 3 Electrical Specification ............................50 AC Timing Diagrams and Test Circuits ......................56 PCB Layout Guideline regarding VDD and AVDD for THCV236-Q ............. 66 Package ................................. 67 Notices and Requests ............................68 THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 3/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 4: Pin Configuration

    (TOP VIEW) CAPOUT MAINMODE/TCMP 65 EXPGND HFSEL/TCMN CAPINA CAPINP LOCKN/MSSEL HTPDN/SUBMODE THCV236-Q (QFN 64pin) HSYNC HTPDN/SUBMODE LOCKN/MSSEL CLKOUT (TOP VIEW) CAPOUT 65 EXPGND CAPINA MAINMODE/RCMN HFSEL/RCMP D24/GPIO3 D25/GPIO4 RXDEFSEL THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 4/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 5: Pin Description

    When GPIO4 is used as Open-Drain Output, it must be connected with a pull-up resistor to VDD. When GPIO4 is used as push pull output or input, no external component is required. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 5/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 6 When GPIO2 is used as Open-Drain Output, it must be connected with a pull-up resistor to VDD. When GPIO2 is used as push pull output or input, no external component is required. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 6/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 7 I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer PWR : Power supply , GND : Ground THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 7/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 8 *4 Programmable GPIO input is default on register setting. *5 Through GPIO open-drain output is default on register setting. *6 Low Speed Data Bridge Mode output is LVCMOS push pull buffer. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 8/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 9 When GPIO0 is used as Open-Drain Output, it must be connected with a pull-up resistor to VDD. When GPIO0 is used as push pull output or input, no external component is required. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 9/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 10 VDD. When GPIO2 is used as push pull output or input, no external component is required. CLKOUT Clock Output D31-D26 12-15,17,18 Pixel Data Output THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 10/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 11 I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer PWR : Power supply , GND : Ground THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 11/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 12 *4 Programmable GPIO input is default on register setting. *5 Through GPIO input is default on register setting. *6 Low Speed Data Bridge Mode output is LVCMOS push pull buffer. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 12/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 13: Functional Overview

    PDN1 and PDN0 turn off internal circuitry of Main-Link and Sub-Link separately. Table 3. Power Down Setting PDN1 PDN0 Operation Both Main-Link and Sub-Link power down Only Main-Link is active Only Sub-Link is active Both Main-Link and Sub-Link active THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 13/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 14: Main-Link Mode Setting

    800mV diff p-p Table 5. Pre-emphasis and Drive Select function table (PDN1=1) Condition CMLDRV[1:0] (register) (register) Swing Level Pre-emphasis Level 400mV diff p-p 600mV diff p-p 3.5dB 800mV diff p-p Forbidden THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 14/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 15: Permanent Clock Output (Thcv236-Q Only)

    SSEN (pin) (Function as HTPDN) 0:SSCG Disable 1:SSCG Enable SSEN (register) SSEN (pin) Table 9. SSCG enable signal (THCV236-Q) PDN1 SUBMODE Mode Entry Signal Description 0:SSCG Disable SSEN(register) 1:SSCG Enable THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 15/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 16 Up to 0.5 % spread at the 30kHz modulation frequency is stable for most cases. In case of using out of this range, please verify at the actual system. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 16/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 17: Data Enable

    DE (tDEH) should always satisfy following equations. tDEH = tTCIP*(2m) tDEINT = tTCIP*(2n) m,n=2,3,4,5,6…… ® Figure 3. Data and Synchronizing Signals Transmission Timing Diagram in V-by-One HS mode THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 17/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 18: Hot-Plug Function

    When PDN1 = 1 (Sub-Link Active), LOCKN is transferred via Sub-Link line. LOCKN/MSSEL pin functions as Sub-Link Master/Slave select (MSSEL). HOST MPU can confirm LOCKN state by reading Sub-Link Master register (0x00 bit1 LOCKN). THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 18/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 19 HTPDN, LOCKN are transmitted via external DC signal. HTPDN, LOCKN are transmitted via Sub-Link. Figure 4. Hot-plug and Lock Detect Scheme when PDN1=0 Figure 5. HTPDN,LOCKN transmission route when PDN1=1 THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 19/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 20: Field Bet Operation

    *3 When PDN0=1, PDN1=0 and BET=1 or PDN0=1, PDN1=1, SUBMODE=1 and BET=1, BET_SEL is set to 0 automatically. *4 Register setting (0x53 bit0, Default 0) Table 17. THCV236-Q Main-Link Field BET Result BETOUT Output Bit Error Occurred No Error THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 20/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 21 *5 Forbidden 0 setting Table 19. Sub-Link Slave device Sub-Link Field BET Result BETOUT Output Bit Error Occurred No Error Figure 6. Main-Link Field BET Configuration Figure 7. Sub-Link Field BET Configuration THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 21/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 22: Data Width And Frequency Range Select Function

    THCV235-Q THCV236-Q Master side Slave side 0x70 0xF0 0x01 Set 1 to PLL_SET_EN 0x76 0xF6 0x02 0x01 Set PLL_SET0 0x78 0xF8 0x20 Set PLL_SET1 0x7C 0xFC 0x24 Set PLL_SET2 THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 22/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 23 16.4 32.5 Color Space Conversion 19.2 Color Space Conversion Color Space Conversion Color Space Conversion Forbidden 133.3 66.6 133.3 Forbidden 16.4 32.5 x100 16.4 32.5 19.2 Forbidden Forbidden Forbidden THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 23/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 24: Data Mapping

    *1 CTL bits, which are carried during DE=0 except the first pixel and the last pixel (when COL1=0) or the first 3pixels and the last 3pixels (when COL1=1). *2 User defined data inputs (THCV235-Q) and outputs (THCV236-Q). THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 24/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 25 HSYNC HSYNC HSYNC HSYNC (*1) VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC (*1) DE/FIELD (*1) *1 Any signal as well as sync signal can be transmitted. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 25/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 26: Sub-Link Mode Setting

    THCV235-Q and THCV236-Q under 2-wire serial interface bus topology. Table 26. 2-wire serial I/F Device ID select (Sub-Link Master device Only) AIN1 AIN0 Device ID 0x0B 0x34 0x77 0x65 THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 26/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 27: 2-Wire Serial I/F Clock Stretching

    When 2WIRE_MODE = 01, Sub-Link Master device informs HOST MPU that Sub-Link Slave register access or remote side 2-wire serial register access has been completed by interruption (INT pin) without clock stretching. Figure 8. 2WIRE_MODE Operation THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 27/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 28: Read/Write Access To Sub-Link Master Register

    Figure 9. Host to Sub-Link Master Register access configuration Figure 10. 2-wire serial I/F write to Sub-Link Master register protocol Figure 11. 2-wire serial I/F read to Sub-Link Master register protocol THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 28/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 29: Read/Write Access To Sub-Link Slave Register

    *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 29/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 30 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 30/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 31: Read/Write Access To Remote Side 2-Wire Serial Slave Devices Connected To Sub-Link Slave Device

    *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 31/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 32 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 32/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 33 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 33/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 34 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 34/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 35: Gpio

    Table 35. GPIO setting of THCV236-Q Function Sub-Link Pin Name Sub-Link Master Slave RXDEFSEL=0 RXDEFSEL=1 D25/GPIO4 GPIO4 D24/GPIO3 GPIO3 COL0/INT/GPIO2 GPIO2 TTLDRV/SD2/AIN0/GPIO1 AIN0 AIN0 GPIO1 LATEN/SD3/AIN1/GPIO0 AIN1 AIN1 GPIO0 THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 35/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 36 Device Number (I:Input, O:Output) Master/Slave Address Value Address Value Input Output GPIO4 GPIO3 (HEX) (BIN) (HEX) (BIN) THCV235-Q Slave 0xC0 XXX11XXX 0xC3 XXX00XXX THCV236-Q Master 0x40 XXX11XXX 0x43 XXX11XXX THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 36/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 37 Value Address Value Input Output GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 (HEX) (BIN) (HEX) (BIN) XXX11XXX XXX10XXX Master 0x40 XXX00XXX 0x43 XXX00XXX XXXXX111 XXXXX101 Slave 0xC0 XXXXX000 0xC3 XXXXX010 XXXXX000 THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 37/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 38: Interruption

    Table 40 (Address 0x02, 0x03) and Table 41 (Address 0x82, 0x83). Figure 16. 2-wire serial I/F Interrupt to HOST access configuration Table 39. Interrupt output State Interrupt occurred Steady state THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 38/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 39: Low Speed Data Bridge Mode

    Sub-Link Slave device is output from SD3 of Sub-Link Master device by LVCMOS push pull output buffer. At Low Speed Data Bridge Mode, access to register of the THCV235-Q and THCV236-Q is unable. Figure 17. Low Speed Data Bridge Mode configuration THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 39/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 40: Register Map

    Sub-Link Slave (2-wire serial master) is connected to external 2-wire serial slave devices. Sub-Link Master device has address 0x00-0x7F, Sub-Link Slave device has address 0x80-0xFF. See Figure 18. Figure 18. Sub-Link Master/Slave device Register Address configuration THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 40/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 41 1: "SLINK_TIMEOUT_INT" is allowed to take action on INT output These registers are always active independent of Interrupt permission register. When No clock stretching mode, the value is 1 fixed, otherwise 0 fixed. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 41/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 42 0x2C RD_START_16B 2-wire serial I/F Read Access Start Trigger for 16bit Register Address device 0x2D-0x3F 0x00 Reserved Assignment of 2-wire serial slave device address connected to Sub-Link Slave outside THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 42/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 43 Reserved. Must be 0 0x00 Reserved 0x8F Reserved 0x90 0x00 Reserved -0xBF Interrupt signal from Sub-Link Slave is reported to Sub-Link Master as Cause of interrupt Sub-Link Slave Side (0x02 bit4 SLAVESIDE_INT). THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 43/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 44 Active only when GPIO is set as input port. Active only when GPIO type is set as "Programmable GPIO" and set as output port. Filter eliminates input glitch shorter than t THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 44/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 45 GPIO0 has only open-drain output buffer. Must be 0 setting GPIO0_OUTBUF_SEL 0: GPIO0 is open-drain output 0x47 0xC7 0x00 Reserved -0x4F -0xCF GPIO input transition is counted as GPIO_INT(0x02 or 0x82 bit3). THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 45/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 46 SSCG PLL setting (*3) 0x7D 0xFD 0xXX Reserved. Must be default setting. -0x7F -0xFF See Table 4 and Table 5 SSEN=1 and SPREAD=0 setting is forbidden See Table 11, Table 21 THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 46/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 47 Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0, RXDEFSEL=0 → default value is 1. Filter eliminates input glitch shorter than t Note that GPIO2_FILT_ENABLE corresponds to Bit#”0”, GPIO0_FILT_ENABLE corresponds to Bit#”2”. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 47/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 48 1: GPIO0 is push pull output 0x47 0xC7 0x00 Reserved -0x4F -0xCF GPIO input transition is counted as GPIO_INT(0x02 or 0x82 bit3). Note that GPIO2_INT_ENABLE corresponds to Bit#”0”, GPIO0_INT_ENABLE corresponds to Bit#”2”. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 48/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 49 SSEN=1 and SPREAD=0 setting is forbidden. Described value is typical value. It has variation in the range from min spec value to max spec value of t See Table 11, Table 21. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 49/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 50: Absolute Maximum Ratings

    Input Leak Current High I,IL VIN=VDD Input Leak Current Low I,IL VIN=0V Output Leak Current High in IOZH O,B,BO VIN=VDD Hi-Z State Output Leak Current Low in IOZL O,B,BO VIN=0V Hi-Z State THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 50/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 51 Ω Bi-Directional Buffer RTERM Termination Resistance Receiver State Ω Bi-Directional Buffer VBOD RDIFF=400Ω Differential Output Voltage Bi-Directional Buffer VBOC VDD-0.3 Common Output Voltage Bi-Directional Buffer TRI-STATE IBOZ PDN1=0 Current THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 51/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 52 PDN0 High to CML Output Delay PDN0 Low to CML Output High tTPLL1 Fix Delay LOCKN High to Training Pattern tTNP0 Output Delay LOCKN Low to Data Pattern tTNP1 Output Delay THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 52/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 53 Bi-Directional Buffer Unit Interval Bi-Directional Buffer tBRF 1000 Rise and Fall Time(20%-80%) Bi-Directional Buffer tBPJTX Transmitter Period Jitter Accuracy (peak to peak) Bi-Directional Buffer tBPJRX Receiver Period Jitter Tolerance (peak to peak) THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 53/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 54 Setup time for STOP condition 386×t SU;STO Bus free time between a STOP and START condition *1 Please adjust Pull-up resistor and bus capacitance to meet the spec value. THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 54/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 55 Programmable GPIO input data hold Table 61. Sub-Link control switching characteristics (Low Speed Data Bridge Mode) Symbol Parameter Unit Low Speed Data input to output delay Low Speed Data input sampling rate LSSR THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 55/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 56 (RF=1) tTCL tTCH (RF=0) (RF=0) RF=0 CLKIN VDD/2 VDD/2 VDD/2 RF=1 D31-D0 HSYNC,VSYNC VDD/2 VDD/2 Figure 19. LVCMOS Input Switching Timing Diagrams Figure 20. LVCMOS Output Switching Timing Diagrams THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 56/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 57 CML Output Switching Characteristics Figure 21. CML Output Switching Characteristics Figure 22. CML Buffer Equivalent Circuit THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 57/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 58 CML Bi-directional Output Test Circuit Figure 23. Bi-directional CML VBOD/VBOC Test Circuit Figure 24. Bi-directional CML Switching Timing Diagram and Test Circuit THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 58/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 59 Latency Characteristics Figure 25. THCV235-Q Latency Figure 26. THCV236-Q Latency THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 59/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 60 Lock and Unlock Sequence Figure 27. THCV235-Q Lock/Unlock Sequence Figure 28. THCV236-Q Lock/Unlock Sequence THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 60/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 61 2-wire serial I/F Switching Characteristics Figure 29. 2-wire serial interface Timing Diagram Figure 30. Write access completion time to Sub-Link Slave register Figure 31. Read access completion time to Sub-Link Slave register THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 61/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 62 Figure 32. Write access completion time to Remote side 2-wire serial slave register Figure 33. Read access completion time to Remote side 2-wire serial slave register THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 62/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 63 Figure 35. Programmable GPIO input timing at Sub-Link Master side Figure 36. Programmable GPIO output timing at Sub-Link Master side Figure 37. Programmable GPIO output timing at Sub-Link Slave side THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 63/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 64 Figure 39. GPIO input and other interrupt event timing at Sub-Link Slave side (Clock Stretching Mode) Figure 39. GPIO input and other interrupt event timing at Sub-Link Slave side (No Clock Stretching Mode) THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 64/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 65 Low Speed Data Bridge Switching Characteristics Figure 40. Low Speed Data Bridge Mode Data Delay THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 65/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 66 GND-through-hole between AVDD and VDD, and separate the distance as possible (Example). Don’t set through-holes next to each other between ferrite beads and AVDD/VDD pins (Bad Example). Good Example 1 Good Example 2 Example Bad Example THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 66/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 67 Package Unit : mm Figure 41. 64-pin QFN package physical dimension THCV235-Q_THCV236-Q_Rev.3.40_E THine Electronics, Inc. 67/68 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 68 Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other.

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Cel serdes thcv236-q

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