Page 1 To our customers, Old Company Name in Catalogs and Other Documents On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document.
Page 2 Notice All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Page 3 User’s Manual RENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp.
Page 4 Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap.
Page 5 4519 Group User’s Manual REVISION HISTORY Rev. Date Description Page Summary 1.00 – First edition issued Aug 06, 2004...
Page 6 BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers.
Page 7: Table Of Contents
Table of contents 4519 Group Table of contents CHAPTER 1 HARDWARE DESCRIPTION ..........................1-2 FEATURES ............................1-2 APPLICATION ..........................1-2 PIN CONFIGURATION ........................1-2 BLOCK DIAGRAM ......................... 1-3 PERFORMANCE OVERVIEW ....................... 1-4 PIN DESCRIPTION ........................1-5 MULTIFUNCTION ........................1-6 DEFINITION OF CLOCK AND CYCLE ................. 1-6 PORT FUNCTION ........................
Page 8 Table of contents 4519 Group CHAPTER 2 APPLICATION 2.1 I/O pins ............................ 2-2 2.1.1 I/O ports .......................... 2-2 2.1.2 Related registers ......................2-6 2.1.3 Port application examples ................... 2-12 2.1.4 Notes on use ........................ 2-13 2.2 Interrupts ..........................2-15 2.2.1 Interrupt functions ......................2-15 2.2.2 Related registers ......................
Page 9 Table of contents 4519 Group CHAPTER 3 APPENDIX 3.1 Electrical characteristics ..................... 3-2 3.1.1 Absolute maximum ratings .................... 3-2 3.1.2 Recommended operating conditions ................3-3 3.1.3 Electrical characteristics ....................3-6 3.1.4 A/D converter recommended operating conditions ............ 3-8 3.1.5 Voltage drop detection circuit characteristics ............3-10 3.1.6 Basic timing diagram ....................
Page 10 List of figures 4519 Group List of figures CHAPTER 1 HARDWARE Fig. 1 AMC instruction execution example ................1-17 Fig. 2 RAR instruction execution example ................1-17 Fig. 3 Registers A, B and register E ..................1-17 Fig. 4 TABP p instruction execution example ................1-17 Fig.
Page 11 List of figures 4519 Group Fig. 48 Internal state at reset 2 ....................1-61 Fig. 49 Voltage drop detection reset circuit ................1-62 Fig. 50 Voltage drop detection circuit operation waveform ............ 1-62 Fig. 51 State transition ........................ 1-65 Fig. 52 Set source and clear source of the P flag ..............1-65 Fig.
Page 12 List of figures 4519 Group Fig. 2.3.15 Count start time and count time when operation starts (PS, T1, T2 and T3) 2-51 Fig. 2.3.16 Count start time and count time when operation starts (T4) ......2-51 Fig. 2.4.1 A/D converter structure ..................... 2-52 Fig.
Page 13 List of figures 4519 Group CHAPTER 3 APPENDIX Fig. 3.3.1 Period measurement circuit program example ............3-16 Fig. 3.3.2 Count start time and count time when operation starts (PS, T1, T2 and T3) .. 3-16 Fig. 3.3.3 Count start time and count time when operation starts (T4) ......3-16 Fig.
Page 14 List of tables 4519 Group List of tables CHAPTER 1 HARDWARE Table Selection of system clock ....................1-6 Table 1 ROM size and pages ....................1-20 Table 2 RAM size ........................1-21 Table 3 Interrupt sources ......................1-22 Table 4 Interrupt request flag, interrupt enable bit and skip instruction ......1-22 Table 5 Interrupt enable bit function ..................
Page 15 List of tables 4519 Group Table 2.3.3 Interrupt control register I1 ..................2-33 Table 2.3.4 Interrupt control register I2 ..................2-33 Table 2.3.5 Timer control register PA ..................2-34 Table 2.3.6 Timer control register W1 ..................2-34 Table 2.3.7 Timer control register W2 ..................2-34 Table 2.3.8 Timer control register W3 ..................
Page 16: Chapter 1 Hardware
CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS CONTROL REGISTERS INSTRUCTIONS BUILT-IN PROM VERSION...
Page 17 The 4519 Group is a 4-bit single-chip microcomputer designed with Key-on wakeup function pins ........... 10 CMOS technology. Its CPU is that of the 4500 series using a Serial I/O ............... 8 bits simple, high-speed instruction set. The computer is equipped with A/D converter ..
Page 18 HARDWARE BLOCK DIAGRAM 4519 Group Block diagram (4519 Group) Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z...
Page 19 HARDWARE PERFORMANCE OVERVIEW 4519 Group PERFORMANCE OVERVIEW Parameter Function Number of basic instructions 0.5 µ s (at 6.0 MHz oscillation frequency, in X Minimum instruction execution time through-mode) Memory sizes M34519M6 6144 words 10 bits M34519M8/E8 8192 words 10 bits M34519M6/M8/E8 384 words 4 bits...
Page 20 HARDWARE PIN DESCRIPTION 4519 Group PIN DESCRIPTION Name Input/Output Function Power supply — Connected to a plus power supply. Ground — Connected to a 0 V power supply. — Connect CNV to V and apply “L” (0V) to CNV certainly. VDCE This pin is used to operate/stop the voltage drop detection circuit.
Page 21: Multifunction
HARDWARE MULTIFUNCTION/DEFINITION OF CLOCK AND CYCLE 4519 Group MULTIFUNCTION Multifunction Multifunction Multifunction Multifunction CNTR0 CNTR0 CNTR1 CNTR1 INT0 INT0 INT1 INT1 Notes 1: Pins except above have just single function. 2: The input/output of P3 and P3 can be used even when INT0 and INT1 are selected. 3: The input of ports P2 –P2 can be used even when S...
Page 22: Port Function
HARDWARE PORT FUNCTION 4519 Group PORT FUNCTION Input Control Control Port Output structure Remark Output unit instructions registers Port D –D N-channel open-drain/ SD, RD Output structure selection FR1, FR2 /CNTR0 CMOS function (programmable) /CNTR1 OP0A Built-in programmable pull-up Port P0 –P0 N-channel open-drain/ CMOS...
Page 23: Connections Of Unused Pins
HARDWARE CONNECTION OF UNUSED PINS 4519 Group CONNECTIONS OF UNUSED PINS Connection Usage condition Open. Internal oscillator is selected. (Note 1) Open. Internal oscillator is selected. (Note 1) RC oscillator is selected. (Note 2) External clock input is selected for main clock. (Note 3) Open.
Page 24: Port Block Diagrams
HARDWARE PORT BLOCK DIAGRAM 4519 Group PORT BLOCK DIAGRAMS Skip decision R e g i s t e r Y Decoder SZD instruction ( N o t e 3 ) C L D (Note 1) i n s t r u c t i o n ( N o t e 2 ) 0 —...
Page 25 HARDWARE PORT BLOCK DIAGRAM 4519 Group Register Y Decoder Skip decision SZD instruction instruction (Note 1) SD instruction /CNTR0 (Note 2) RD instruction Timer 1 underflow signal Timer 2 underflow signal Clock (input) for timer 1 event count or period measurement signal input Register Y Decoder Skip decision...
Page 26 HARDWARE PORT BLOCK DIAGRAM 4519 Group (Note 3) IAP0 instruction Register A Pull-up transistor (Note 1) (Note 3) , P0 (Note 2) (Note 1) OP0A instruction Level detection circuit Key-on wakeup Edge detection circuit (Note 4) IAP0 instruction Register A Pull-up transistor (Note 1)
Page 27 HARDWARE PORT BLOCK DIAGRAM 4519 Group IAP2 instruction R e g i s t e r A (Note 1) ( N o t e 2 ) OP2A instruction S y n c h r o n o u s c l o c k ( o u t p u t ) f o r s e r i a l d a t a t r a n s f e r S y n c h r o n o u s c l o c k ( i n p u t ) f o r s e r i a l d a t a t r a n s f e r...
Page 28 HARDWARE PORT BLOCK DIAGRAM 4519 Group IAP3 instruction Register A (Note 1) /INT0 (Note 2) OP3A instruction (Note 3) External 0 interrupt External 0 interrupt circuit Key-on wakeup input Timer 1 count start synchronous circuit input Period measurement circuit input IAP3 instruction Register A (Note 1)
Page 29 HARDWARE PORT BLOCK DIAGRAM 4519 Group (Note 3) IAP4 instruction Register A (Note 1) –P4 (Note 2) OP4A instruction Decoder Analog input (Note 3) Register A IAP5 instruction (Note 3) (Note 1) –P5 (Note 2) OP5A instruction Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be V or less.
Page 30 HARDWARE PORT BLOCK DIAGRAM 4519 Group ( N o t e 3 ) I A P 6 i n s t r u c t i o n R e g i s t e r A ( N o t e 1 ) , P 6 I N 0 I N 1...
Page 31 HARDWARE PORT BLOCK DIAGRAM 4519 Group One-sided edge (Note 1) Falling detection circuit External 0 /INT0 EXF0 interrupt Period measurement Both edges Rising circuit input detection circuit Timer 1 count start synchronous circuit (Note 2) Level detection circuit Key-on wakeup (Note 3) Edge detection circuit Skip decision...
Page 32: Function Block Operations
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group FUNCTION BLOCK OPERATIONS <Carry> (CY) (1) Arithmetic logic unit (ALU) ( M ( D P ) ) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4- A L U Addition bit data addition, comparison, AND operation, OR operation, and bit manipulation.
Page 33: Fig. 5 Stack Registers (Sks) Structure
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (5) Stack registers (SK ) and stack pointer (SP) Program counter (PC) Stack registers (SKs) are used to temporarily store the contents of E x e c u t i n g B M E x e c u t i n g R T program counter (PC) just before branching until returning to the i n s t r u c t i o n...
Page 34: Fig. 7 Program Counter (Pc) Structure
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (8) Program counter (PC) P r o g r a m c o u n t e r Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read.
Page 35: Program Memory (Rom)
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed 8 7 6 5 4 3 2 1 of 10 bits. ROM is separated every 128 words by the unit of page 0000 (addresses 0 to 127).
Page 36: Data Memory (Ram)
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group DATA MEMORY (RAM) Table 2 RAM size 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with Part number RAM size the SB j, RB j, and SZB j instructions) is enabled for the entire M34519M6 384 words 4 bits (1536 bits)
Page 37: Interrupt Function
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group INTERRUPT FUNCTION Table 3 Interrupt sources Priority Interrupt The interrupt type is a vectored interrupt branching to an individual Interrupt name Activated condition level address address (interrupt address) according to each interrupt source. An External 0 interrupt Level change of Address 0...
Page 38: Fig. 13 Program Example Of Interrupt Processing
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (4) Internal state during an interrupt • Program counter (PC) The internal state of the microcomputer during an interrupt is as fol- ............... Each interrupt address lows (Figure 14). • Program counter (PC) • Stack register (SK) An interrupt address is set in program counter.
Page 39: Table 6 Interrupt Control Registers
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.
Page 40: Fig. 16 Interrupt Sequence
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Fig. 16 Interrupt sequence 1-25 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z...
Page 41: External Interrupts
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group EXTERNAL INTERRUPTS The 4519 Group has the external 0 interrupt and external 1 inter- rupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2.
Page 42 HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (1) External 0 interrupt request flag (EXF0) (2) External 1 interrupt request flag (EXF1) External 0 interrupt request flag (EXF0) is set to “1” when a valid External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to P3 /INT0 pin.
Page 43: Table 8 External Interrupt Control Register
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (3) External interrupt control registers • Interrupt control register I2 Register I2 controls the valid waveform for the external 1 inter- • Interrupt control register I1 rupt. Set the contents of this register through register A with the Register I1 controls the valid waveform for the external 0 inter- TI2A instruction.
Page 44: Fig. 18 External 0 Interrupt Program Example-1
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (4) Notes on External 0 interrupt Note on bit 2 of register I1 When the interrupt valid waveform of the P3 /INT0 pin is Note [1] on bit 3 of register I1 changed with the bit 2 of register I1 in software, be careful about When the input of the INT0 pin is controlled with the bit 3 of reg- the following notes.
Page 45: Fig. 21 External 1 Interrupt Program Example-1
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (5) Notes on External 1 interrupt Note on bit 2 of register I2 Note [1] on bit 3 of register I2 When the interrupt valid waveform of the P3 /INT1 pin is When the input of the INT1 pin is controlled with the bit 3 of reg- changed with the bit 2 of register I2 in software, be careful about ister I2 in software, be careful about the following notes.
Page 46: Timers
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group TIMERS • Fixed dividing frequency timer The 4519 Group has the following timers. The fixed dividing frequency timer has the fixed frequency divid- • Programmable timer ing ratio (n). An interrupt request flag is set to “1” after every n The programmable timer has a reload register and enables the count of a count pulse.
Page 47: Table 9 Function Related Timers
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Table 9 Function related timers Frequency Control Circuit Structure Count source Use of output signal dividing ratio register • Instruction clock (INSTCK) Prescaler 8-bit programmable 1 to 256 • Timer 1, 2, 3, amd 4 count sources binary down counter Timer 1 8-bit programmable...
Page 48: Fig. 25 Timer Structure (1)
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group , MR System clock (STCK) Division circuit Divided by 8 Internal clock Divided by 4 Instruction clock On-chip oscillator generating circuit (INSTCK) Divided by 2 (divided by 3) Ceramic resonance Multi- RC oscillation plexer Quartz-crystal (CMCK, oscillation...
Page 49: Fig. 26 Timer Structure (2)
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group One-sided edge / I N T 1 detection circuit (Note 4) Both edges detection circuit T 3 U D F , W 3 T i m e r 3 Timer 3 (8) PWMOUT T 3 F i n t e r r u p t O R C L K T2UDF...
Page 50: Table 10 Timer Related Registers
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Table 10 Timer related registers Timer control register PA at reset : 0 at RAM back-up : 0 TPAA Stop (state initialized) Prescaler control bit Operating Timer control register W1 at reset : 0000 at RAM back-up : state retained TAW1/TW1A Timer 1 count auto-stop circuit not selected...
Page 51 HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Timer control register W4 at reset : 0000 at RAM back-up : 0000 TAW4/TW4A (I/O) / CNTR1 (input) /CNTR1 pin function selection bit CNTR1 (I/O) / D (input) PWM signal “H” interval expansion function invalid PWM signal “H”...
Page 52 HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (1) Timer control registers (2) Prescaler • Timer control register PA Prescaler is an 8-bit binary down counter with the prescaler reload Register PA controls the count operation of prescaler. Set the register PRS. Data can be set simultaneously in prescaler and the contents of this register through register A with the TPAA instruc- reload register RPS with the TPSAB instruction.
Page 53 HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (6) Timer 4 (interrupt function) (4) Timer 2 (interrupt function) Timer 4 is an 8-bit binary down counter with two timer 4 reload reg- Timer 2 is an 8-bit binary down counter with the timer 2 reload reg- isters (R4L, R4H).
Page 54: Fig. 27 Period Measurement Circuit Program Example
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (7) Period measurement function (Timer 1, In addition, execute the SNZT1 instruction to clear the T1F flag period measurement circuit) after executing at least one instruction (refer to Figure 27 ). Also, set the NOP instruction for the case when a skip is per- Timer 1 has the period measurement circuit which performs timer formed with the SNZT1 instruction (refer to Figure 27 ).
Page 55 HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (9) Count start synchronization circuit (timer 1, (11) Timer input/output pin timer 3) /CNTR0 pin, D /CNTR1 pin) Timer 1 and timer 3 have the count start synchronous circuit which CNTR0 pin is used to input the timer 1 count source and output the synchronizes the input of INT0 pin and INT1 pin, and can start the timer 1 and timer 2 underflow signal divided by 2.
Page 56: Fig. 28 Period Measurement Circuit Program Example
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (13) Timer interrupt request flags Depending on the state of timer 1, the timer 1 interrupt request (T1F, T2F, T3F, T4F) flag (T1F) may be set to “1” when the period measurement cir- cuit is stopped by clearing bit 2 of register W5 to “0”. In order to Each timer interrupt request flag is set to “1”...
Page 57: Fig. 29 Timer 4 Operation
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group CNTR1 output: invalid (W4 = “0”) Timer 4 count source Timer 4 count value (R4L) (Reload (R4L) register) (R4L) (R4L) (R4L) Timer 4 underflow signal PWM signal (output invalid) PWM signal “L” Timer 4 start fixed CNTR1 output: valid (W4 = “1”)
Page 58 HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group CNTR1 output auto-control circuit by timer 3 is selected. CNTR1 output: valid (W4 = “1”) CNTR1 output auto-control circuit selected (W6 = “1”) signal Timer 3 underflow signal Timer 3 start CNTR1 output CNTR1 output start CNTR1 output auto-control function signal Timer 3 underflow signal...
Page 59: Fig. 31 Timer 4 Count Start/Stop Timing
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Waveform extension function of CNTR1 output “H” interval: Invalid (W4 = “0”), CNTR1 output: valid (W4 = “1”), Count source: X input selected (W4 = “0”), Reload register R4L: “03 ” Reload register R4H: “02 ”...
Page 60: Watchdog Timer
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group WATCHDOG TIMER Watchdog timer provides a method to reset the system when a pro- When the WEF flag is set to “1” after system is released from reset, gram run-away occurs. Watchdog timer consists of timer the watchdog timer function is valid.
Page 61: Fig. 33 Program Example To Start/Stop Watchdog Timer
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group When the watchdog timer is used, clear the WDF1 flag at the pe- riod of 65534 machine cycles or less with the WRST instruction. WRST ; WDF1 flag cleared When the watchdog timer is not used, execute the DWDT instruc- tion and the WRST instruction continuously (refer to Figure 33).
Page 62: A/D Converter (Comparator)
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group A/D CONVERTER (Comparator) Table 11 A/D converter characteristics Parameter Characteristics The 4519 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 Conversion format Successive comparison method shows the characteristics of this A/D converter.
Page 63: Table 12 A/D Control Registers
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Table 12 A/D control registers A/D control register Q1 at reset : 0000 at RAM back-up : state retained TAQ1/TQ1A A/D conversion mode A/D operation mode selection bit Comparator mode Analog input pins Analog input pin selection bits A/D control register Q2 at RAM back-up : state retained at reset : 0000...
Page 64: Table 13 Change Of Successive Comparison Register Ad During A/D Conversion
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (4) A/D conversion completion flag (ADF) (1) A/D control register A/D conversion completion flag (ADF) is set to “1” when A/D con- • A/D control register Q1 version completes. The state of ADF flag can be examined with the Register Q1 controls the selection of A/D operation mode and the skip instruction (SNZAD).
Page 65: Fig. 36 A/D Conversion Timing Chart
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (7) A/D conversion timing chart Figure 36 shows the A/D conversion timing chart. ADST instruction 2 machine cycles + 10/f(ADCK) A/D conversion completion flag (ADF) DAC operation signal Fig. 36 A/D conversion timing chart (Bit 3) (Bit 0) (8) How to use A/D conversion...
Page 66: Fig. 38 Comparator Operation Timing Chart
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (9) Operation at comparator mode (12) Comparator operation start instruction (ADST instruction) The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to “1.” In comparator mode, executing ADST starts the comparator oper- Below, the operation at comparator mode is described.
Page 67: Fig. 39 Definition Of A/D Conversion Accuracy
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (14) Definition of A/D converter accuracy Vn: Analog input voltage when the output data changes from “n” to The A/D conversion accuracy is defined below (refer to Figure 39). “n+1” (n = 0 to 1022) –V •...
Page 68: Serial I/O
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group SERIAL I/O Table 14 Serial I/O pins The 4519 Group has a built-in clock synchronous serial I/O which Pin function when selecting serial I/O can serially transmit or receive 8-bit data. Clock I/O (S Serial I/O consists of;...
Page 69: Fig. 41 Serial I/O Register State When Transferring
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group At transmit (D –D : transfer data) At receive p i n p i n O U T Serial I/O register (SI) S e r i a l I / O r e g i s t e r ( S I ) p i n p i n O U T...
Page 70: Fig. 42 Serial I/O Connection Example
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (5) How to use serial I/O wiring between each pin with a resistor. Figure 42 shows the data Figure 42 shows the serial I/O connection example. Serial I/O inter- transfer timing and Table 16 shows the data transfer sequence. rupt is not used in this example.
Page 71: Fig. 43 Timing Of Serial I/O Data Transfer
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Master ’ O U T ’ S S T i n s t r u c t i o n S l a v e S S T i n s t r u c t i o n s i g n a l R D Y ’...
Page 72: Table 16 Processing Sequence Of Data Transfer From Master To Slave
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Table 16 Processing sequence of data transfer from master to slave Master (transmission) Slave (reception) [Initial setting] [Initial setting] • Setting the serial I/O mode register J1 and inter- • Setting serial I/O mode register J1, and interrupt control register V2 shown in rupt control register V2 shown in Figure 42.
Page 73: Reset Function
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group RESET FUNCTION System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions.
Page 74: Fig. 46 Structure Of Reset Pin And Its Peripherals, And Power-On Reset Operation
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group If the rising time exceeds 100 µs, connect a capacitor between the (1) Power-on reset Reset can be automatically performed at power on (power-on re- RESET pin and V at the shortest distance, and input “L” level to set) by the built-in power-on reset circuit.
Page 75 HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (2) Internal state at reset Figure 47 and 48 show internal state at reset (they are the same af- ter system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure are undefined, so set the initial value to them.
Page 76 HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group • Port output structure control register FR0 ................• Port output structure control register FR1 ................• Port output structure control register FR2 ................• Port output structure control register FR3 ................• Carry flag (CY) ........................•...
Page 77: Voltage Drop Detection Circuit
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. VDCE Voltage drop detection circuit –...
Page 78: Ram Back-Up Mode
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group RAM BACK-UP MODE Table 19 Functions and states retained at RAM back-up The 4519 Group has the RAM back-up mode. Function RAM back-up When the EPOF and POF instructions are executed continuously, Program counter (PC), registers A, B, system enters the RAM back-up state.
Page 79: Table 20 Return Source And Return Condition
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (4) Return signal • Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transis- An external wakeup signal is used to return from the RAM back-up tor. Set the contents of this register through register A with the mode because the oscillation is stopped.
Page 80: Fig. 51 State Transition
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (Note 5) Key-on wakeup RAM back-up mode Operation state Reset • Operation source clock: POF instruction (Note 1) f(RING) execution • f(X ): Stop (Note 4) ←1 ←0 (Note 2) Operation state • Operation source clock: POF instruction f(RING) execution...
Page 81: Table 21 Key-On Wakeup Control Register, Pull-Up Control Register
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Table 21 Key-on wakeup control register, pull-up control register Key-on wakeup control register K0 at reset : 0000 at RAM back-up : state retained TAK0/TK0A Pins P1 and P1 key-on wakeup Key-on wakeup not used control bit Key-on wakeup used Pins P1...
Page 82: Table 22 Key-On Wakeup Control Register, Pull-Up Control Register
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group Table 22 Key-on wakeup control register, pull-up control register Pull-up control register PU0 at reset : 0000 at RAM back-up : state retained TAPU0/ TPU0A pin pull-up transistor Pull-up transistor OFF control bit Pull-up transistor ON pin pull-up transistor Pull-up transistor OFF control bit...
Page 83: Clock Control
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group CLOCK CONTROL The CMCK, CRCK, and CYCK instructions can be used only to se- The clock control circuit consists of the following circuits. lect main clock (f(X )). In this time, the start of oscillation and the •...
Page 84: Fig. 55 Switch To Ceramic Resonance/Rc Oscillation/Quartz-Crystal Oscillation
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (1) Main clock generating circuit (f(X The ceramic resonator, RC oscillation or quartz-crystal oscillator can be used for the main clock of this MCU. After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal os- cillator.
Page 85: Fig. 56 Handling Of
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (2) On-chip oscillator operation M34519 Do not use the CMCK, CRCK and When the MCU operates by the on-chip oscillator as the main clock CYCK instructions in program. (f(X )) without using the ceramic resonator, RC oscillator or quartz-crystal oscillation, leave X pin and X pin open (Figure...
Page 86: Rom Ordering Method
HARDWARE FUNCTION BLOCK OPERATIONS 4519 Group (7) Clock control register MR (8) Clock control register RG Register MR controls system clock. Set the contents of this register Register RG controls start/stop of on-chip oscillator. Set the con- through register A with the TMRA instruction. In addition, the TAMR tents of this register through register A with the TRGA instruction.
Page 87: List Of Precautions
HARDWARE LIST OF PRECAUTIONS 4519 Group LIST OF PRECAUTIONS Prescaler Stop counting and then execute the TABPS instruction to read Noise and latch-up prevention from prescaler data. Connect a capacitor on the following condition to prevent noise Stop counting and then execute the TPSAB instruction to set and latch-up;...
Page 88: Fig. 61 Period Measurement Circuit Program Example
HARDWARE LIST OF PRECAUTIONS 4519 Group Period measurement circuit When a period measurement circuit is used, clear bit 0 of regis- ter I1 to “0”, and set a timer 1 count start synchronous circuit to be “not selected”. Start timer operation immediately after operation of a period measurement circuit is started.
Page 89: Fig. 62 External 0 Interrupt Program Example-1
HARDWARE LIST OF PRECAUTIONS 4519 Group /INT0 pin Note on bit 2 of register I1 Note [1] on bit 3 of register I1 When the interrupt valid waveform of the P3 /INT0 pin is When the input of the INT0 pin is controlled with the bit 3 of reg- changed with the bit 2 of register I1 in software, be careful about ister I1 in software, be careful about the following notes.
Page 90: Fig. 65 External 1 Interrupt Program Example-1
HARDWARE LIST OF PRECAUTIONS 4519 Group Note on bit 2 of register I2 /INT1 pin When the interrupt valid waveform of the P3 /INT1 pin is Note [1] on bit 3 of register I2 changed with the bit 2 of register I2 in software, be careful about When the input of the INT1 pin is controlled with the bit 3 of reg- the following notes.
Page 91: Fig. 68 A/D Converter Program Example-3
HARDWARE LIST OF PRECAUTIONS 4519 Group A/D converter-1 POF instruction • When the TALA instruction is executed, the low-order 2 bits of When the POF instruction is executed continuously after the register AD is transferred to the high-order 2 bits of register A, si- EPOF instruction, system enters the RAM back-up state.
Page 92 HARDWARE LIST OF PRECAUTIONS 4519 Group External clock When the external clock signal for the main clock (f(X )) is used, connect the clock source to X pin and X pin open. In pro- gram, after the CMCK instruction is executed, set main clock (f(X )) oscillation start to be enabled (MR =0).
Page 93: Control Registers
HARDWARE CONTROL REGISTERS 4519 Group CONTROL REGISTERS Interrupt control register V1 at reset : 0000 at RAM back-up : 0000 TAV1/TV1A Interrupt disabled (SNZT2 instruction is valid) Timer 2 interrupt enable bit Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Timer 1 interrupt enable bit Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid)
Page 94 HARDWARE CONTROL REGISTERS 4519 Group TAMR/ Clock control register MR at reset : 1111 at RAM back-up : 1111 TMRA Operation mode Through mode (frequency not divided) Operation mode selection bits Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode Main clock (f(X )) oscillation enabled...
Page 95 HARDWARE CONTROL REGISTERS 4519 Group Timer control register W3 at reset : 0000 at RAM back-up : state retained TAW3/TW3A Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selection bit (Note 2) Timer 3 count auto-stop circuit selected Stop (state retained) Timer 3 control bit Operating...
Page 96 HARDWARE CONTROL REGISTERS 4519 Group Serial I/O control register J1 at reset : 0000 at RAM back-up : state retained TAJ1/TJ1A Synchronous clock Instruction clock (INSTCK) divided by 8 Serial I/O synchronous clock selection bits Instruction clock (INSTCK) divided by 4 Instruction clock (INSTCK) divided by 2 External clock (S input)
Page 97 HARDWARE CONTROL REGISTERS 4519 Group Key-on wakeup control register K0 at reset : 0000 at RAM back-up : state retained TAK0/TK0A Pins P1 and P1 key-on wakeup Key-on wakeup not used control bit Key-on wakeup used Pins P1 and P1 key-on wakeup Key-on wakeup not used control bit...
Page 98 HARDWARE CONTROL REGISTERS 4519 Group Pull-up control register PU0 at reset : 0000 at RAM back-up : state retained TAPU0/ TPU0A pin pull-up transistor Pull-up transistor OFF control bit Pull-up transistor ON pin pull-up transistor Pull-up transistor OFF control bit Pull-up transistor ON pin pull-up transistor Pull-up transistor OFF...
Page 99 HARDWARE CONTROL REGISTERS 4519 Group Port output structure control register FR0 at reset : 0000 at RAM back-up : state retained TFR0A Ports P1 , P1 output structure selection N-channel open-drain output CMOS output Ports P1 , P1 output structure selection N-channel open-drain output CMOS output Ports P0...
Page 100: Instructions
HARDWARE INSTRUCTIONS 4519 Group INSTRUCTIONS SYMBOL The 4519 Group has the 153 instructions. Each instruction is de- The symbols shown below are used in the following list of instruc- scribed as follows; tion function and the machine instructions. (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table...
Page 101: Index List Of Instruction Function
HARDWARE INDEX OF INSTRUCTION FUNCTION 4519 Group INDEX LIST OF INSTRUCTION FUNCTION Group- Group- Mnemonic Function Page Mnemonic Function Page (A) ← (B) (A) ← → (M(DP)) 110, 130 XAMI j 129, 130 (X) ← (X)EXOR(j) (B) ← (A) 119, 130 j = 0 to 15 (Y) ←...
Page 102 HARDWARE INDEX OF INSTRUCTION FUNCTION 4519 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- Group- Mnemonic Function Page Mnemonic Function Page (Mj(DP)) ← 1 (INTE) ← 0 SB j 103, 132 95, 136 j = 0 to 3 (INTE) ← 1 95, 136 (Mj(DP)) ←...
Page 103 HARDWARE INDEX OF INSTRUCTION FUNCTION 4519 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- Group- Mnemonic Function Page Mnemonic Function Page (A) ← (W4) ) ← (B) 109, 138 TAW4 118, 136 T4HAB (R4H –R4H ) ← (A) (R4H –R4H (W4) ←...
Page 104 HARDWARE INDEX OF INSTRUCTION FUNCTION 4519 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- Group- Mnemonic Function Page Mnemonic Function Page (D) ← 1 (B) ← (SI ) (A) ← (SI 93, 140 TABSI –SI –SI 112, 142 (D(Y)) ← 0 ) ←...
Page 105 HARDWARE INDEX OF INSTRUCTION FUNCTION 4519 Group INDEX LIST OF INSTRUCTION FUNCTION (continued) Group- Mnemonic Function Page (PC) ← (PC) + 1 99, 144 Transition to RAM back-up mode 101, 144 EPOF POF instruction valid 96, 144 SNZP (P) = 1 ? 105, 144 DWDT Stop of watchdog timer function...
Page 106: Machine Instructions (Index By Alphabet)
HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – Overflow = 0 (A) ← (A) + n Operation: Grouping: Arithmetic operation...
Page 107 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) AND (logical AND between accumulator and memory) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (A) AND (M(DP)) Grouping: Arithmetic operation Operation:...
Page 108 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) BM a (Branch and Mark to address a in page 2) Instruction Number of Number of Flag CY Skip condition words cycles code – – (SP) ← (SP) + 1 Grouping: Subroutine call operation Operation:...
Page 109 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) CMA (CoMplement of Accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (A) Operation: Grouping: Arithmetic operation Description: Stores the one’s complement for register A’s contents in register A.
Page 110 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) DEY (DEcrement register Y) Instruction Number of Number of Flag CY Skip condition words cycles code – (Y) = 15 (Y) ← (Y) – 1 Operation: Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y.
Page 111 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) EPOF (Enable POF instruction) Instruction Number of Number of Flag CY Skip condition words cycles code – – Grouping: Other operation Operation: POF instruction valid Description: Makes the immediate after POF instruction valid by executing the EPOF instruction.
Page 112 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) IAP3 (Input Accumulator from port P3) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (P3) Operation: Grouping: Input/Output operation Description: Transfers the input of port P3 to register A.
Page 113 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) INY (INcrement register Y) Instruction Number of Number of Flag CY Skip condition words cycles code – (Y) = 0 (Y) ← (Y) + 1 Operation: Grouping: RAM addresses Description: Adds 1 to the contents of register Y.
Page 114 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) NOP (No OPeration) Instruction Number of Number of Flag CY Skip condition words cycles code – – (PC) ← (PC) + 1 Operation: Grouping: Other operation Description: No operation;...
Page 115 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OP3A (Output port P3 from Accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – – (P3) ← (A) Operation: Grouping: Input/Output operation Description: Outputs the contents of register A to port OP4A (Output port P4 from Accumulator) Number of...
Page 116 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) OR (logical OR between accumulator and memory) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (A) OR (M(DP)) Operation: Grouping: Arithmetic operation...
Page 117 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RC (Reset Carry flag) Instruction Number of Number of Flag CY Skip condition words cycles code – (CY) ← 0 Operation: Grouping: Arithmetic operation Description: Clears (0) to carry flag CY. RD (Reset port D specified by register Y) Number of Number of...
Page 118 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) RTS (ReTurn from subroutine and Skip) Instruction Number of Number of Flag CY Skip condition words cycles code – Skip at uncondition (PC) ← (SK(SP)) Grouping: Return operation Operation: (SP) ←...
Page 119 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SEA n (Skip Equal, Accumulator with immediate data n) Instruction Number of Number of Flag CY Skip condition words cycles code – (A) = n Grouping: Comparison operation Description: Skips the next instruction when the con- Operation:...
Page 120 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZAD (Skip if Non Zero condition of A/D conversion completion flag) Instruction Number of Number of Flag CY Skip condition words cycles code – = 0: (ADF) = 1 Operation: = 0: (ADF) = 1 ? Grouping:...
Page 121 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZSI (Skip if Non Zero condition of Serial I/o interrupt request flag) Instruction Number of Number of Flag CY Skip condition words cycles code – = 0: (SIOF) = 1 Operation: = 0: (SIOF) = 1 ? Grouping:...
Page 122 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SNZT4 (Skip if Non Zero condition of Timer 4 inerrupt request flag) Instruction Number of Number of Flag CY Skip condition words cycles code – = 0: (T4F) = 1 Operation: = 0: (T4F) = 1 ? Grouping:...
Page 123 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) SZC (Skip if Zero, Carry flag) Instruction Number of Number of Flag CY Skip condition words cycles code – (CY) = 0 Operation: (CY) = 0 ? Grouping: Arithmetic operation Description: Skips the next instruction when the con-...
Page 124 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B) Instruction Number of Number of Flag CY Skip condition words cycles code –...
Page 125 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB (Transfer data to Accumulator from register B) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (B) Operation: Grouping: Register to register transfer Description: Transfers the contents of register B to reg-...
Page 126 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAB4 (Transfer data to Accumulator and register B from timer 4) Instruction Number of Number of Flag CY Skip condition words cycles code – – (B) ← (T4 Operation: –T4 Grouping:...
Page 127 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TABPS (Transfer data to Accumulator and register B from PreScaler) Instruction Number of Number of Flag CY Skip condition words cycles code – – (B) ← (TPS Operation: –TPS Grouping:...
Page 128 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAI1 (Transfer data to Accumulator from register I1) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (I1) Operation: Grouping: Interrupt operation Description: Transfers the contents of interrupt control...
Page 129 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAK1 (Transfer data to Accumulator from register K1) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (K1) Grouping: Input/Output operation Operation: Description: Transfers the contents of key-on wakeup...
Page 130 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAMR (Transfer data to Accumulator from register MR) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (MR) Grouping: Clock operation Operation: Description: Transfers the contents of clock control reg-...
Page 131 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAQ2 (Transfer data to Accumulator from register Q2) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (Q2) Operation: Grouping: A/D conversion operation Description: Transfers the contents of A/D control regis-...
Page 132 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAV2 (Transfer data to Accumulator from register V2) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (V2) Operation: Grouping: Interrupt operation Description: Transfers the contents of interrupt control...
Page 133 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAW4 (Transfer data to Accumulator from register W4) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (W4) Operation: Grouping: Timer operation Description: Transfers the contents of timer control reg-...
Page 134 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TAY (Transfer data to Accumulator from register Y) Instruction Number of Number of Flag CY Skip condition words cycles code – – (A) ← (Y) Operation: Grouping: Register to register transfer Description: Transfers the contents of register Y to regis-...
Page 135 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TEAB (Transfer data to register E from Accumulator and register B) Instruction Number of Number of Flag CY Skip condition words cycles code – – ) ← (B) Operation: –E Grouping:...
Page 136 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TFR3A (Transfer data to register FR3 from Accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – – (FR3) ← (A) Operation: Grouping: Input/Output operation Description: Transfers the contents of register A to the...
Page 137 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TK0A (Transfer data to register K0 from Accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – – (K0) ← (A) Operation: Grouping: Input/Output operation Description: Transfers the contents of register A to key-...
Page 138 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TMRA (Transfer data to register MR from Accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – – (MR) ← (A) Operation: Grouping: Other operation Description: Transfers the contents of register A to clock...
Page 139 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TPU1A (Transfer data to register PU1 from Accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – – (PU1) ← (A) Operation: Grouping: Input/Output operation Description: Transfers the contents of register A to pull-...
Page 140 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TR1AB (Transfer data to register R1 from Accumulator and register B) Instruction Number of Number of Flag CY Skip condition words cycles code – – ) ← (B) Operation: –R1 Grouping:...
Page 141 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TV1A (Transfer data to register V1 from Accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – – (V1) ← (A) Grouping: Interrupt operation Operation: Description: Transfers the contents of register A to inter-...
Page 142 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TW3A (Transfer data to register W3 from Accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – – (W3) ← (A) Operation: Grouping: Timer operation Description: Transfers the contents of register A to timer...
Page 143 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) TYA (Transfer data to register Y from Accumulator) Instruction Number of Number of Flag CY Skip condition words cycles code – – (Y) ← (A) Operation: Grouping: Register to register transfer Description: Transfers the contents of register A to regis-...
Page 144 HARDWARE MACHINE INSTRUCTIONS (INDEX BY ALPHABET) 4519 Group MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued) XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) Number of Flag CY Instruction Instruction Instruction Number of Number of Number of Flag CY Skip condition Skip condition...
Page 145: Machine Instructions (Index By Types)
HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) Instruction code Parameter Function Mnemonic Hexadecimal Type of notation instructions (A) ← (B) 0 1 E (B) ← (A) 0 0 E (A) ← (Y) 0 1 F (Y) ←...
Page 146 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group Skip condition Datailed description – – Transfers the contents of register B to register A. – – Transfers the contents of register A to register B. – – Transfers the contents of register Y to register A. –...
Page 147 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Instruction code Parameter Function Mnemonic Hexadecimal Type of notation instructions (A) ← n LA n 0 7 n n = 0 to 15 (SP) ← (SP) + 1 TABP p 0 8 p (SK(SP)) ←...
Page 148 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group Skip condition Datailed description Continuous – Loads the value n in the immediate field to register A. description When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped.
Page 149 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Instruction code Parameter Function Mnemonic Hexadecimal Type of notation instructions ) ← a 1 8 a –a ) ← p (Note) BL p, a 0 E p ) ←...
Page 150 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group Skip condition Datailed description – – Branch within a page : Branches to address a in the identical page. – – Branch out of a page : Branches to address a in page p. Branch out of a page : Branches to address (DR specified by registers D and A in –...
Page 151 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Instruction code Parameter Function Mnemonic Hexadecimal Type of notation instructions (INTE) ← 0 0 0 4 (INTE) ← 1 0 0 5 SNZ0 0 3 8 = 0: (EXF0) = 1 ? After skipping, (EXF0) ←...
Page 152 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group Skip condition Datailed description – – Clears (0) to interrupt enable flag INTE, and disables the interrupt. – – Sets (1) to interrupt enable flag INTE, and enables the interrupt. = 0: (EXF0) = 1 –...
Page 153 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Instruction code Parameter Function Mnemonic Hexadecimal Type of notation instructions (A) ← (W5) 2 4 F TAW5 (W5) ← (A) 2 1 2 TW5A (A) ← (W6) 2 5 0 TAW6 (W6) ←...
Page 154 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group Skip condition Datailed description – – Transfers the contents of timer control register W5 to register A. – – Transfers the contents of register A to timer control register W5. – – Transfers the contents of timer control register W6 to register A.
Page 155 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Instruction code Parameter Function Mnemonic Hexadecimal Type of notation instructions = 0: (T1F) = 1 ? After skipping, (T1F) ← 0 SNZT1 2 8 0 = 0: NOP = 0: (T2F) = 1 ? After skipping, (T2F) ←...
Page 156 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group Skip condition Datailed description = 0: (T1F) = 1 – Skips the next instruction when the contents of bit 2 (V1 ) of interrupt control register V1 is “0” and the con- tents of T1F flag is “1.”...
Page 157 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Instruction code Parameter Function Mnemonic Hexadecimal Type of notation instructions (A) ← (K0) TAK0 2 5 6 (K0) ← (A) TK0A 2 1 B (A) ← (K1) TAK1 2 5 9 (K1) ←...
Page 158 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group Skip condition Datailed description – – Transfers the contents of key-on wakeup control register K0 to register A. – – Transfers the contents of register A to key-on wakeup control register K0 . –...
Page 159 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued) Instruction code Parameter Function Mnemonic Hexadecimal Type of notation instructions TABAD 2 7 9 = 0: (B) ← (AD –AD (A) ← (AD –AD = 1: (B) ←...
Page 160 HARDWARE MACHINE INSTRUCTIONS (INDEX BY TYPES) 4519 Group Skip condition Datailed description – – In the A/D conversion mode (Q1 = 0), transfers the high-order 4 bits (AD –AD ) of register AD to register B, and the middle-order 4 bits (AD –AD ) of register AD to register A.
Page 161: Instruction Code Table
HARDWARE INSTRUCTION CODE TABLE 4519 Group INSTRUCTION CODE TABLE 010000 011000 –D 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011001100 001101 001110 001111 010111 011111 Hex. 10–17 18–1F –D notation TABP TABP TABP TABP 0000 BMLA –...
Page 162 HARDWARE INSTRUCTION CODE TABLE 4519 Group INSTRUCTION CODE TABLE (continued) 110000 –D 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 111111 Hex. 30–3F –D notation XAMI XAMD – TW3A OP0A T1AB – TAW6 IAP0 TAB1...
Page 163: Built-In Prom Version
HARDWARE BUILT-IN PROM VERSION 4519 Group BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4519 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM.
Page 164: Fig. 73 Flow Of Writing And Test Of The Product Shipped In Blank
HARDWARE BUILT-IN PROM VERSION 4519 Group Table 25 Programming adapter (1) PROM mode Microcomputer Name of Programming Adapter The built-in PROM version has a PROM mode in addition to a nor- M34519E8FP PCA7441 mal operation mode. The PROM mode is used to write to and read from the built-in PROM.
Page 165: Chapter 2 Application
CHAPTER 2 APPLICATION 2.1 I/O pins 2.2 Interrupts 2.3 Timers 2.4 A/D converter 2.5 Serial I/O 2.6 Reset 2.7 Voltage drop detection circuit 2.8 RAM back-up 2.9 Oscillation circuit...
Page 166: I/O Ports
APPLICATION 2.1 I/O pins 4519 Group 2.1 I/O pins The 4519 Group has thirty-five I/O pins. Port P2 is also used as Serial I/O pins S Port P3 is also used as INT0 input pin. Port P3 is also used as INT1 input pin. Port P4 is also used as analog input pins A –A Port P6 is also used as analog input pins A...
Page 167: Chapter 2 Application
APPLICATION 2.1 I/O pins 4519 Group (3) Port P2 Port P2 is a 3-bit I/O port. –P2 are also used as serial I/O pins S Input In the following condition, the pin state of port P2 is transferred as input data to register A when the IAP2 instruction is executed.
Page 168 APPLICATION 2.1 I/O pins 4519 Group Port P4 –P4 are also used as analog input pins A –A Input In the following conditions, the pin state of port P4 is transferred as input data to register A when the IAP4 instruction is executed. •...
Page 169 APPLICATION 2.1 I/O pins 4519 Group (8) Port D Ports D –D are eight independent I/O ports. Port D is also used as CNTR0 I/O pin. Port D is also used as CNTR1 I/O pin. Input/output of port D Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D –D , select one of port D with the register Y of the data pointer first.
Page 170: Related Registers
APPLICATION 2.1 I/O pins 4519 Group 2.1.2 Related registers (1) Timer control register W4 Table 2.1.1 shows the timer control register W4. Set the contents of this register through register A with the TW4A instruction. The contents of register W4 is transferred to register A with the TAW4 instruction. Table 2.1.1 Timer control register W4 Timer control register W4 at reset : 0000...
Page 171: Table 2.1.3 Serial I/O Control Register J1
APPLICATION 2.1 I/O pins 4519 Group (3) Serial I/O control register J1 Table 2.1.3 shows the serial I/O control register J1. Set the contents of this register through register A with the TJ1A instruction. The contents of register J1 is transferred to register A with the TAJ1 instruction. Table 2.1.3 Serial I/O control register J1 at RAM back-up : state retained Serial I/O control register J1...
Page 172: Table 2.1.5 Pull-Up Control Register Pu0
APPLICATION 2.1 I/O pins 4519 Group (5) Pull-up control register PU0 Table 2.1.5 shows the pull-up control register PU0. Set the contents of this register through register A with the TPU0A instruction. The contents of register PU0 is transferred to register A with the TAPU0 instruction. Table 2.1.5 Pull-up control register PU0 Pull-up control register PU0 at reset : 0000...
Page 173: Table 2.1.7 Port Output Structure Control Register Fr0
APPLICATION 2.1 I/O pins 4519 Group (7) Port output structure control register FR0 Table 2.1.7 shows the port output structure control register FR0. Set the contents of this register through register A with the TFR0A instruction. Table 2.1.7 Port output structure control register FR0 Port output structure control register FR0 at reset : 0000 at RAM back-up : state retained...
Page 174: Table 2.1.9 Port Output Structure Control Register Fr2
APPLICATION 2.1 I/O pins 4519 Group (9) Port output structure control register FR2 Table 2.1.9 shows the port output structure control register FR2. Set the contents of this register through register A with the TFR2A instruction. Table 2.1.9 Port output structure control register FR2 Port output structure control register FR2 at reset : 0000 at RAM back-up : state retained...
Page 175: Table 2.1.11 Key-On Wakeup Control Register K0
APPLICATION 2.1 I/O pins 4519 Group (11) Key-on wakeup control register K0 Table 2.1.11 shows the key-on wakeup control register K0. Set the contents of this register through register A with the TK0A instruction. The contents of register K0 is transferred to register A with the TAK0 instruction. Table 2.1.11 Key-on wakeup control register K0 at RAM back-up : state retained Key-on wakeup control register K0...
Page 176: Port Application Examples
APPLICATION 2.1 I/O pins 4519 Group 2.1.3 Port application examples (1) Key input by key scan Key matrix can be set up by connecting keys externally because port D output structure is an N- channel open-drain and port P0 has the pull-up resistor. Outline: The connecting required external part is just keys.
Page 177: Notes On Use
APPLICATION 2.1 I/O pins 4519 Group 2.1.4 Notes on use (1) Note when an I/O port is used as an input port Set the output latch to “1” and input the port value before input. If the output latch is set to “0”, “L” level can be input.
Page 178: Table 2.1.13 Connections Of Unused Pins
APPLICATION 2.1 I/O pins 4519 Group Table 2.1.13 Connections of unused pins Connection Usage condition Open. Internal oscillator is selected. (Note 1) Open. Internal oscillator is selected. (Note 1) RC oscillator is selected. (Note 2) External clock input is selected for main clock. (Note 3) –D Open.
Page 179: Interrupts
APPLICATION 2.2 Interrupts 4519 Group 2.2 Interrupts The 4519 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 4, A/ D and serial I/O. This section describes individual types of interrupts, related registers, application examples using interrupts and notes.
Page 180 APPLICATION 2.2 Interrupts 4519 Group (4) Timer 2 interrupt The interrupt request occurs by the timer 2 underflow. Timer 2 interrupt processing When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to “1.”...
Page 181 APPLICATION 2.2 Interrupts 4519 Group (7) A/D interrupt The interrupt request occurs by the completion of A/D conversion. A/D interrupt processing When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the interrupt enable flag INTE are set to “1.”...
Page 182: Related Registers
APPLICATION 2.2 Interrupts 4519 Group 2.2.2 Related registers (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0”...
Page 183: Table 2.2.2 Interrupt Control Register V2
APPLICATION 2.2 Interrupts 4519 Group (4) Interrupt control register V2 Table 2.2.2 shows the interrupt control register V2. Set the contents of this register through register A with the TV2A instruction. In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 2.2.2 Interrupt control register V2 Interrupt control register V2 at reset : 0000...
Page 184: Table 2.2.4 Interrupt Control Register I2
APPLICATION 2.2 Interrupts 4519 Group (6) Interrupt control register I2 Table 2.2.4 shows the interrupt control register I2. Set the contents of this register through register A with the TI2A instruction. In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A. Table 2.2.4 Interrupt control register I2 Interrupt control register I2 at reset : 0000...
Page 185: Interrupt Application Examples
APPLICATION 2.2 Interrupts 4519 Group 2.2.3 Interrupt application examples (1) External 0 interrupt The INT0 pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can recognize the change of falling edge (“H”→“L”), rising edge (“L”→“H”) and both edges (“H”→“L” or “L”→“H”).
Page 186: Fig. 2.2.1 External 0 Interrupt Operation Example
APPLICATION 2.2 Interrupts 4519 Group (5) Timer 3 interrupt Constant period interrupts by a setting value to timer 3 can be used. Outline: The constant period interrupts by the timer 3 underflow signal can be used. Specifications: Prescaler and timer 3 divide the system clock frequency = 6.0 MHz, and the timer 3 interrupt occurs every 1 ms.
Page 187: Fig. 2.2.2 External 0 Interrupt Setting Example
APPLICATION 2.2 Interrupts 4519 Group Disable Interrupts External 0 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b0: External 0 interrupt occurrence disabled [TV1A] ↓ ↓ ↓ ↓ ↓ Set Port Port used for external 0 interrupt is set to input port. Port P3 output latch Set to input [OP3A]...
Page 188: Fig. 2.2.3 External 1 Interrupt Operation Example
APPLICATION 2.2 Interrupts 4519 Group “H” /INT1 “L” “H” An interrupt occurs after the valid waveform “falling” is detected. /INT1 “L” Fig. 2.2.3 External 1 interrupt operation example 2-24 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z...
Page 189: Fig. 2.2.4 External 1 Interrupt Setting Example
APPLICATION 2.2 Interrupts 4519 Group Disable Interrupts External 1 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b1: External 1 interrupt occurrence disabled [TV1A] ↓ ↓ ↓ ↓ ↓ Set Port Port used for external 1 interrupt is set to input port. Port P3 output latch Set to input [OP3A]...
Page 190: Fig. 2.2.5 Timer 1 Constant Period Interrupt Setting Example
APPLICATION 2.2 Interrupts 4519 Group Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b2: Timer 1 interrupt occurrence disabled [TV1A] ↓ ↓ ↓ ↓ ↓ Stop Timer Operation Timer 1 is temporarily stopped.
Page 191: Fig. 2.2.6 Timer 2 Constant Period Interrupt Setting Example
APPLICATION 2.2 Interrupts 4519 Group Disable Interrupts Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b3: Timer 2 interrupt occurrence disabled [TV1A] ↓ ↓ ↓ ↓ ↓ Stop Timer and Prescaler Operation Timer 2 and prescaler are temporarily stopped.
Page 192: Fig. 2.2.7 Timer 3 Constant Period Interrupt Setting Example
APPLICATION 2.2 Interrupts 4519 Group Disable Interrupts Timer 3 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V2 b0: Timer 3 interrupt occurrence disabled [TV2A] ↓ ↓ ↓ ↓ ↓ Stop Timer Operation Timer 3 and prescaler are temporarily stopped.
Page 193: Fig. 2.2.8 Timer 4 Constant Period Interrupt Setting Example
APPLICATION 2.2 Interrupts 4519 Group Disable Interrupts Timer 4 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V2 b1: Timer 4 interrupt occurrence disabled [TV2A] ↓ ↓ ↓ ↓ ↓ Stop Timer and Prescaler Operation [TW4A] Timer 4 and prescaler are temporarily stopped.
Page 194: Notes On Use
APPLICATION 2.2 Interrupts 4519 Group 2.2.4 Notes on use (1) Setting of INT0 interrupt valid waveform Set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction. Depending on the input state of P3 /INT0 pin, the external interrupt request flag (EXF0) may be set to “1”...
Page 195: Timers
APPLICATION 2.3 Timers 4519 Group 2.3 Timers The 4519 Group has four 8-bit timers (each has a reload register) and the watchdog timer function. This section describes individual types of timers, related registers, application examples using timers and notes. 2.3.1 Timer functions (1) Timer 1 Timer operation (Timer 1 has the timer 1 count start trigger function from P3...
Page 196: Related Registers
APPLICATION 2.3 Timers 4519 Group 2.3.2 Related registers (1) Interrupt control register V1 Table 2.3.1 shows the interrupt control register V1. Set the contents of this register through register A with the TV1A instruction. In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 2.3.1 Interrupt control register V1 Interrupt control register V1 at reset : 0000...
Page 197: Table 2.3.3 Interrupt Control Register I1
APPLICATION 2.3 Timers 4519 Group (3) Interrupt control register I1 Table 2.3.3 shows the interrupt control register I1. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 2.3.3 Interrupt control register I1 Interrupt control register I1 at reset : 0000...
Page 198: Table 2.3.5 Timer Control Register Pa
APPLICATION 2.3 Timers 4519 Group (5) Timer control register PA Table 2.3.5 shows the timer control register PA. Set the contents of this register through register A with the TPAA instruction. Table 2.3.5 Timer control register PA Timer control register PA at reset : 0 at RAM back-up : state retained Stop (state initialized)
Page 199: Table 2.3.8 Timer Control Register W3
APPLICATION 2.3 Timers 4519 Group (8) Timer control register W3 Table 2.3.8 shows the timer control register W3. Set the contents of this register through register A with the TW3A instruction. In addition, the TAW3 instruction can be used to transfer the contents of register W3 to register A. Table 2.3.8 Timer control register W3 Timer control register W3 at reset : 0000...
Page 200: Table 2.3.10 Timer Control Register W5
APPLICATION 2.3 Timers 4519 Group (10) Timer control register W5 Table 2.3.10 shows the timer control register W5. Set the contents of this register through register A with the TW5A instruction. In addition, the TAW5 instruction can be used to transfer the contents of register W5 to register A. Table 2.3.10 Timer control register W5 Timer control register W5 at reset : 0000...
Page 201: Timer Application Examples
APPLICATION 2.3 Timers 4519 Group 2.3.3 Timer application examples (1) Timer operation: measurement of constant period The constant period by the setting timer count value can be measured. Outline: The constant period by the timer 1 underflow signal can be measured. Specifications: Timer 1 and prescaler divide the system clock frequency f(X ) = 4.0 MHz, and the timer 1 interrupt occurs every 3 ms.
Page 202: Fig. 2.3.2 Timer 4 Operation
APPLICATION 2.3 Timers 4519 Group (4) Timer operation: timer start by external input Outline: The constant period can be measured by external input. Specifications: Timer 3 operates by INT1 input as a trigger and an interrupt occurs after 1 ms. Figure 2.3.7 shows the setting example of timer start.
Page 203: Fig. 2.3.3 Watchdog Timer Function
APPLICATION 2.3 Timers 4519 Group (8) Watchdog timer Watchdog timer provides a method to reset the system when a program run-away occurs. Accordingly, when the watchdog timer function is set to be valid, execute the WRST instruction at a certain period which consists of 16-bit timers’ 65534 counts or less (execute WRST instruction at less than 65534 machine cycles).
Page 204: Fig. 2.3.4 Constant Period Measurement Setting Example
APPLICATION 2.3 Timers 4519 Group Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b2: Timer 1 interrupt occurrence disabled [TV1A] ↓ ↓ ↓ ↓ ↓ Stop Timer and Prescaler Operation Timer 1 and prescaler are temporarily stopped.
Page 205: Fig. 2.3.5 Cntr0 Output Setting Example
APPLICATION 2.3 Timers 4519 Group Disable Interrupts Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b3: Timer 2 interrupt occurrence disabled [TV1A] ↓ ↓ ↓ ↓ ↓ Stop Timer and Prescaler Operation Timer 2 and prescaler are temporarily stopped.
Page 206: Fig. 2.3.6 Cntr0 Input Setting Example
APPLICATION 2.3 Timers 4519 Group Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b2: Timer 1 interrupt occurrence disabled [TV1A] ↓ ↓ ↓ ↓ ↓ Stop Timer Operation Timer 1 is temporarily stopped.
Page 207: Fig. 2.3.7 Timer Start By External Input Setting Example
APPLICATION 2.3 Timers 4519 Group Disable Interrupts Timer 3 interrupt and external interrupt are temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b1: External 1 interrupt occurrence disabled [TV1A] Interrupt control register V2 b0: Timer 3 interrupt occurrence disabled [TV2A] ↓...
Page 208: Fig. 2.3.8 Pwm Output Control Setting Example
APPLICATION 2.3 Timers 4519 Group Disable Interrupts (Note 1) Timer 4 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V2 b1: Timer 4 interrupt occurrence disabled [TV2A] ↓ ↓ ↓ ↓ ↓ Stop Timer Operation Timer 4 is temporarily stopped.
Page 209 APPLICATION 2.3 Timers 4519 Group Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b2: Timer 1 interrupt occurrence disabled [TV1A] ↓ ↓ ↓ ↓ ↓ Stop Timer Operation Timer 1 interrupt is temporarily disabled.
Page 210 APPLICATION 2.3 Timers 4519 Group Timer 1 interrupt occurrence (period measurement completed) ↓ ↓ ↓ ↓ ↓ Stop Timer Operation Timer 1 interrupt is disabled. [TW1A] Timer control register W1 b2: Timer 1 stop ↓ ↓ ↓ ↓ ↓ Disable Interrupts Timer 1 interrupt is disabled.
Page 211 APPLICATION 2.3 Timers 4519 Group Disable Interrupts Timer 1 interrupt and External 0 interrupt are temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V1 b2, b0: Timer 1 interrupt and External 0 interrupt occurrence disabled [TV1A] ↓...
Page 212 APPLICATION 2.3 Timers 4519 Group Timer 1 interrupt occurrence (period measurement completed) ↓ ↓ ↓ ↓ ↓ Stop Timer Operation Timer 1 interrupt is disabled. [TW1A] Timer control register W1 b2: Timer 1 stop ↓ ↓ ↓ ↓ ↓ Disable Interrupts Timer 1 interrupt is disabled.
Page 213: Fig. 2.3.13 Watchdog Timer Setting Example
APPLICATION 2.3 Timers 4519 Group Main Routine (every 20 ms) Reset Flag WDF1 Watchdog timer flag WDF1 is reset. Watchdog timer flag WDF1 cleared. [WRST] ↓ ↓ ↓ ↓ ↓ Note when the watchdog timer flag is cleared When is executed, considering the skip of the next instruction according to the watchdog timer flag WDF1, insert the NOP instruction after the WRST instruction.
Page 214: Notes On Use
APPLICATION 2.3 Timers 4519 Group 2.3.4 Notes on use (1) Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. (2) Count source Stop timer 1, 2, 3, 4 or LC counting to change its count source. (3) Reading the count values Stop timer 1, 2, 3 or 4 counting and then execute the TAB1, TAB2, TAB3 or TAB4 instruction to read its data.
Page 215: Fig. 2.3.14 Period Measurement Circuit Program Example
APPLICATION 2.3 Timers 4519 Group When the signal for period measurement is D /CNTR0 pin input, do not select D /CNTR0 pin input as timer 1 count source. (The X input is recommended as timer 1 count source at the time of period measurement circuit use.) When the input of P3 /INT0 pin is selected for measurement, set the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be enabled.
Page 216: A/D Converter
APPLICATION 2.4 A/D converter 4519 Group 2.4 A/D converter The 4519 Group has an 8-channel A/D converter with the 10-bit successive comparison method. This A/D converter can also be used as a comparator to compare analog voltages input from the analog input pin with preset values.
Page 217: Related Registers
APPLICATION 2.4 A/D converter 4519 Group 2.4.1 Related registers (1) Interrupt control register V2 Table 2.4.1 shows the interrupt control register V2. Set the contents of this register through register A with the TV2A instruction. In addition, the TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 2.4.1 Interrupt control register V2 Interrupt control register V2 at reset : 0000...
Page 218: A/D Converter Application Examples
APPLICATION 2.4 A/D converter 4519 Group (3) A/D control register Q2 Table 2.4.3 shows the A/D control register Q2. Set the contents of this register through register A with the TQ2A instruction. The contents of register Q2 is transferred to register A with the TAQ2 instruction. Table 2.4.3 A/D control register Q2 A/D control register Q2 at reset : 0000...
Page 219: Fig. 2.4.2 A/D Conversion Mode Setting Example
APPLICATION 2.4 A/D converter 4519 Group Disable Interrupts A/D interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V2 b2: A/D interrupt occurrence disabled [TV2A] ↓ ↓ ↓ ↓ ↓ Set A/D Converter A/D conversion mode is selected to A/D operation mode. Analog input pin A is selected.
Page 220: Notes On Use
APPLICATION 2.4 A/D converter 4519 Group 2.4.3 Notes on use (1) Note when the A/D conversion starts again When the A/D conversion starts again with the ADST instruction during A/D conversion, the previous input data is invalidated and the A/D conversion starts again. (2) A/D converter-1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage.
Page 221 APPLICATION 2.4 A/D converter 4519 Group (5) A/D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains “0,” not set to “1.” In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled.
Page 222: Serial I/O
APPLICATION 2.5 Serial I/O 4519 Group 2.5 Serial I/O The 4519 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit data. This section describes serial I/O functions, related registers, application examples using serial I/O and notes.
Page 223: Related Registers
APPLICATION 2.5 Serial I/O 4519 Group 2.5.2 Related registers (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. Also, the low-order 4 bits of register SI is transferred to register A, and the high-order 4 bits of register SI is transferred to register B with the TABSI instruction.
Page 224: Operation Description
APPLICATION 2.5 Serial I/O 4519 Group 2.5.3 Operation description Figure 2.5.2 shows the serial I/O connection example, Figure 2.5.3 shows the serial I/O register state, and Figure 2.5.4 shows the serial I/O transfer timing. Master (internal clock selected) Slave (external clock selected) 4519 4519 Control signal...
Page 225: Fig. 2.5.4 Serial I/O Transfer Timing
APPLICATION 2.5 Serial I/O 4519 Group Master ’ ’ SST instruction Slave SST instruction Control signal ’ ’ –M : Contents of master serial I/O register –S : Contents of slave serial I/O register Rising of S : Serial input Falling of S : Serial output ’, S...
Page 226 APPLICATION 2.5 Serial I/O 4519 Group The full duplex communication of master and slave is described using the connection example shown in Figure 2.5.2. (1) Transmit/receive operation of master Set the transmit data to the serial I/O register SI with the TSIAB instruction. When the TSIAB instruction is executed, the contents of register A are transferred to the low-order 4 bits of register SI and the contents of register B are transferred to the high-order 4 bits of register Check whether the microcomputer on the slave side is ready to transmit/receive or not.
Page 227: Serial I/O Application Example
APPLICATION 2.5 Serial I/O 4519 Group (2) Transmit/receive operation of slave Set the transmit data into the serial I/O register SI with the TSIAB instruction. When the TSIAB instruction is executed, the contents of register A are transferred to the low- order bits of register SI and the contents of register B are transferred to the high-order bits of register SI.
Page 228: Fig. 2.5.5 Setting Example When A Serial I/O Of Master Side Is Not Used
APPLICATION 2.5 Serial I/O 4519 Group Disable Interrupts (Note) Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V2 b3: Serial I/O interrupt occurrence disabled [TV2A] ↓ ↓ ↓ ↓ ↓ Set Port Port for control signal is set to input.
Page 229: Fig. 2.5.6 Setting Example When A Serial I/O Interrupt Of Slave Side Is Used
APPLICATION 2.5 Serial I/O 4519 Group Disable Interrupts Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE All interrupts disabled [DI] Interrupt control register V2 b3: Serial I/O interrupt occurrence disabled [TV2A] ↓ ↓ ↓ ↓ ↓ Set Port Port for control signal is set to “H”...
Page 230: Notes On Use
APPLICATION 2.5 Serial I/O 4519 Group 2.5.5 Notes on use (1) Note when an external clock is used as a synchronous clock: • An external clock is selected as the synchronous clock, the clock is not controlled internally. • Serial transmit/receive is continued as long as an external clock is input. If an external clock is input 9 times or more and serial transmit/receive is continued, the receive data is transferred directly as transmit data, so that be sure to control the clock externally.
Page 231: Reset
APPLICATION 2.6 Reset 4519 Group 2.6 Reset System reset is performed by applying “L” level to pin for 1 machine cycle or more when the the RESET following conditions are satisfied: the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H”...
Page 232: Internal State At Reset
APPLICATION 2.6 Reset 4519 Group 2.6.2 Internal state at reset Figure 2.6.3 and Figure 2.6.4 show the internal state at reset. The contents of timers, registers, flags and RAM other than shown in Figure 2.6.3 and Figure 2.6.4 are undefined, so that set them to initial values. •...
Page 233: Notes On Use
APPLICATION 2.6 Reset 4519 Group • Key-on wakeup control register K0 ............0 0 0 0 • Key-on wakeup control register K1 ............0 0 0 0 • Key-on wakeup control register K2 ............0 0 0 0 • Pull-up control register PU0 ............... 0 0 0 0 •...
Page 234: Voltage Drop Detection Circuit
APPLICATION 2.7 Voltage drop detection circuit 4519 Group 2.7 Voltage drop detection circuit The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Figure 2.7.1 shows the voltage drop detection circuit, and Figure 2.7.2 shows the operation waveform example of the voltage drop detection circuit.
Page 235: Ram Back-Up
APPLICATION 2.8 RAM back-up 4519 Group 2.8 RAM back-up The 4519 Group has the RAM back-up mode. Figure 2.8.1 shows the state transition. (Note 5) Key-on wakeup RAM back-up mode Operation state Reset • Operation source clock: POF instruction (Note 1) f(RING) execution •...
Page 236: Table 2.8.1 Functions And States Retained At Ram Back-Up Mode
APPLICATION 2.8 RAM back-up 4519 Group Table 2.8.1 Functions and states retained at RAM back-up mode Function RAM back-up Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control registers I1, I2 Selected oscillation circuit Clock control register MR...
Page 237: Fig. 2.8.2 Start Condition Identified Example
APPLICATION 2.8 RAM back-up 4519 Group Table 2.8.2 Return source and return condition Return source Return condition Remarks Ports P0 –P0 Return by an external “H” level The key-on wakeup function can be selected with 2 or “L” level input, or rising edge port units.
Page 238: Related Registers
APPLICATION 2.8 RAM back-up 4519 Group 2.8.2 Related registers (1) Interrupt control register I1 Table 2.8.4 shows the interrupt control register I1. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 2.8.4 Interrupt control register I1 Interrupt control register I1 at reset : 0000...
Page 239: Table 2.8.6 Pull-Up Control Register Pu0
APPLICATION 2.8 RAM back-up 4519 Group (3) Pull-up control register PU0 Table 2.8.6 shows the pull-up control register PU0. Set the contents of this register through register A with the TPU0A instruction. The contents of register PU0 is transferred to register A with the TAPU0 instruction. Table 2.8.6 Pull-up control register PU0 Pull-up control register PU0 at reset : 0000...
Page 240: Table 2.8.7 Pull-Up Control Register Pu1
APPLICATION 2.8 RAM back-up 4519 Group (4) Pull-up control register PU1 Table 2.8.7 shows the pull-up control register PU1. Set the contents of this register through register A with the TPU1A instruction. The contents of register PU1 is transferred to register A with the TAPU1 instruction. Table 2.8.7 Pull-up control register PU1 Pull-up control register PU1 at reset : 0000...
Page 241: Table 2.8.9 Key-On Wakeup Control Register K1
APPLICATION 2.8 RAM back-up 4519 Group (6) Key-on wakeup control register K1 Table 2.8.9 shows the key-on wakeup control register K1. Set the contents of this register through register A with the TK1A instruction. The contents of register K1 is transferred to register A with the TAK1 instruction. Table 2.8.9 Key-on wakeup control register K1 Key-on wakeup control register K1 at reset : 0000...
Page 242: Notes On Use
APPLICATION 2.8 RAM back-up 4519 Group 2.8.3 Notes on use (1) POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction.
Page 243: Oscillation Circuit
APPLICATION 2.9 Oscillation circuit 4519 Group 2.9 Oscillation circuit The 4519 Group has an internal oscillation circuit to produce the clock required for microcomputer operation. The 4519 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset.
Page 244: Related Register
APPLICATION 2.9 Oscillation circuit 4519 Group 2.9.2 Related register (1) Clock control register MR Table 2.9.1 shows the clock control register MR. Set the contents of this register through register A with the TMRA instruction. The contents of register MR is transferred to register A with the TAMR instruction. Table 2.9.1 Clock control register MR Clock control register MR at reset : 1111...
Page 245 APPLICATION 2.9 Oscillation circuit 4519 Group 2.9.3 Notes on use (1) Clock control Execute the main clock (f(X )) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once.
Page 246: Chapter 3 Appendix
CHAPTER 3 APPENDIX 3.1 Electrical characteristics 3.2 Typical characteristics 3.3 List of precautions 3.4 Notes on noise 3.5 Package outline...
Page 247: Absolute Maximum Ratings
APPENDIX 3.1 Electrical characteristics 4519 Group 3.1 Electrical characteristics 3.1.1 Absolute maximum ratings Table 3.1.1 Absolute maximum ratings Parameter Symbol Conditions Ratings Unit Supply voltage –0.3 to 6.5 Input voltage –0.3 to V +0.3 P0, P1, P2, P3, P4, P5, P6, D –D , RESET, X , VDCE...
Page 248: Recommended Operating Conditions
APPENDIX 3.1 Electrical characteristics 4519 Group 3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions 1 (Mask ROM version: Ta = –20 °C to 85 °C, V = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, V = 2.5 to 5.5 V, unless otherwise noted) Limits Symbol...
Page 249: Electrical Characteristics
APPENDIX 3.1 Electrical characteristics 4519 Group Table 3.1.3 Recommended operating conditions 2 (Mask ROM version: Ta = –20 °C to 85 °C, V = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, V = 2.5 to 5.5 V, unless otherwise noted) Limits Symbol...
Page 250 APPENDIX 3.1 Electrical characteristics 4519 Group Table 3.1.4 Recommended operating conditions 3 (Mask ROM version: Ta = –20 °C to 85 °C, V = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, V = 2.5 to 5.5 V, unless otherwise noted) Limits Symbol...
Page 251: Chapter 3 Appendix
APPENDIX 3.1 Electrical characteristics 4519 Group 3.1.3 Electrical characteristics Table 3.1.5 Electrical characteristics 1 (Mask ROM version: Ta = –20 °C to 85 °C, V = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, V = 2.5 to 5.5 V, unless otherwise noted) Limits Symbol...
Page 252: Table 3.1.6 Electrical Characteristics 2
APPENDIX 3.1 Electrical characteristics 4519 Group Table 3.1.6 Electrical characteristics 2 (Mask ROM version: Ta = –20 °C to 85 °C, V = 1.8 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = –20 °C to 85 °C, V = 2.5 to 5.5 V, unless otherwise noted) Limits Symbol...
Page 253: A/D Converter Recommended Operating Conditions
APPENDIX 3.1 Electrical characteristics 4519 Group 3.1.4 A/D converter recommended operating conditions Table 3.1.7 A/D converter recommended operating conditions (Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted) Limits Symbol Parameter Conditions Unit Typ. Min. Max. Supply voltage Mask ROM version One Time PROM version...
Page 254: Table 3.1.8 A/D Converter Characteristics
APPENDIX 3.1 Electrical characteristics 4519 Group Table 3.1.8 A/D converter characteristics (Ta = –20 °C to 85 °C, unless otherwise noted) Limits Unit Symbol Parameter Test conditions Typ. Max. Min. – bits Resolution 2.7 (3.0) V ≤ V ≤ 5.5 V((): One Time PROM version) –...
Page 255: Voltage Drop Detection Circuit Characteristics
APPENDIX 3.1 Electrical characteristics 4519 Group 3.1.5 Voltage drop detection circuit characteristics Table 3.1.9 Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. Detection voltage Ta = 25 °C RST–...
Page 256: Typical Characteristics
APPENDIX 3.2 Typical characteristics 4519 Group 3.2 Typical characteristics As for the standard characteristics, refer to “Renesas Technology Corp.” Homepage. http://www.renesas.com/en/720 3-11 Rev.1.00 Aug 06, 2004 REJ09B0175-0100Z...
Page 257: List Of Precautions
APPENDIX 3.3 List of precautions 4519 Group 3.3 List of precautions 3.3.1 Program counter Make sure that the PC does not specify after the last page of the built-in ROM. 3.3.2 Stack registers (SK Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction.
Page 258: Table 3.3.1 Connections Of Unused Pins
APPENDIX 3.3 List of precautions 4519 Group Table 3.3.1 Connections of unused pins Connection Usage condition Open. Internal oscillator is selected. (Note 1) Open. Internal oscillator is selected. (Note 1) RC oscillator is selected. (Note 2) External clock input is selected for main clock. (Note 3) –D Open.
Page 259: Notes On Interrupt
APPENDIX 3.3 List of precautions 4519 Group 3.3.4 Notes on interrupt (1) Setting of INT0 interrupt valid waveform Set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction. Depending on the input state of P3 /INT0 pin, the external interrupt request flag (EXF0) may be set to “1”...
Page 260: Notes On Timer
APPENDIX 3.3 List of precautions 4519 Group 3.3.5 Notes on timer (1) Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. (2) Count source Stop timer 1, 2, 3, 4 or LC counting to change its count source.
Page 261: Fig. 3.3.1 Period Measurement Circuit Program Example
APPENDIX 3.3 List of precautions 4519 Group When the signal for period measurement is D /CNTR0 pin input, do not select D /CNTR0 pin input as timer 1 count source. (The X input is recommended as timer 1 count source at the time of period measurement circuit use.) When the input of P3 /INT0 pin is selected for measurement, set the bit 3 of a register I1 to “1”, and set the input of INT0 pin to be enabled.
Page 262: Notes On A/D Conversion
APPENDIX 3.3 List of precautions 4519 Group 3.3.6 Notes on A/D conversion (1) Note when the A/D conversion starts again When the A/D conversion starts again with the ADST instruction during A/D conversion, the previous input data is invalidated and the A/D conversion starts again. (2) A/D converter-1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage.
Page 263: Notes On Serial I/O
APPENDIX 3.3 List of precautions 4519 Group (5) A/D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains “0,” not set to “1.” In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled.
Page 264: Notes On Ram Back-Up
APPENDIX 3.3 List of precautions 4519 Group 3.3.9 Notes on RAM back-up (1) POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back-up state. Note that system cannot enter the RAM back-up state when executing only the POF instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF instruction.
Page 265: Notes On Clock Control
APPENDIX 3.3 List of precautions 4519 Group 3.3.10 Notes on clock control (1) Clock control Execute the main clock (f(X )) selection instruction (CMCK, CRCK or CYCK instruction) in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CMCK, CRCK or CYCK instruction can be selected only at once.
Page 266: Notes On Noise
APPENDIX 3.4 Notes on noise 4519 Group (2) Wiring for RESET input pin 3.4 Notes on noise Make the length of wiring which is connected Countermeasures against noise are described below. to the RESET input pin as short as possible. The following countermeasures are effective against Especially, connect a capacitor across the noise in theory, however, it is necessary not only to...
Page 267: Fig. 3.4.3 Wiring For Clock I/O Pins
APPENDIX 3.4 Notes on noise 4519 Group (3) Wiring for clock input/output pins (4) Wiring to CNV • Make the length of wiring which is connected Connect the CNV pin to the V pin with to clock I/O pins as short as possible. the shortest possible wiring.
Page 268: Connection Of Bypass Capacitor Across
APPENDIX 3.4 Notes on noise 4519 Group (5) Wiring to V pin of built-in PROM version 3.4.2 Connection of bypass capacitor across V In the built-in PROM version of the 4524 Group, line and V line Connect an approximately 0.1 µ F bypass capacitor the CNV pin is also used as the built-in PROM power supply input pin V...
Page 269: Wiring To Analog Input Pins
APPENDIX 3.4 Notes on noise 4519 Group 3.4.3 Wiring to analog input pins 3.4.4 Oscillator concerns • Connect an approximately 100 Ω to 1 kΩ resistor Take care to prevent an oscillator that generates to an analog signal line which is connected to an clocks for a microcomputer operation from being analog input pin in series.
Page 270: Setup For I/O Ports
APPENDIX 3.4 Notes on noise 4519 Group (2) Installing oscillator away from signal lines 3.4.5 Setup for I/O ports where potential levels change frequently Setup I/O ports using hardware and software as Install an oscillator and a connecting pattern follows: of an oscillator away from signal lines where <Hardware>...
Page 271: Fig. 3.4.11 Watchdog Timer By Software
APPENDIX 3.4 Notes on noise 4519 Group <The main routine> • Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: (Counts of interrupt processing executed in N+1≥...
Page 272: Package Outline
APPENDIX 3.5 Package outline 4519 Group 3.5 Package outline 42P2R-A Recommended Plastic 42pin 450mil SSOP EIAJ Package Code Weight(g) Lead Material JEDEC Code SSOP42-P-450-0.80 – 0.63 Alloy 42/Cu Alloy Recommended Mount Pad Dimension in Millimeters Symbol – – – – –...
Page 273 RENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER USER’S MANUAL 4519 Group Publication Data : Rev.1.00 Aug 08, 2004 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 274 4519 Group User’s Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0175-0100Z...

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Renkforce 4500 Series User Manual

Chapter 1 Hardware

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Chapter 3 Appendix

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