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Summary of Contents for PLX Technology PEX 8647-AA
- Page 1 PEX 8647-AA Quick Start Hardware Design Guide Version 1.2 January, 2008 Website: www.plxtech.com Support: www.plxtech.com/support Phone: 800 759-3735 408 774-9060 Fax: 408 774-2169...
- Page 2 © 2007 – 2008 PLX Technology, Inc. All Rights Reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
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Page 3: Table Of Contents
Table 2. PEX 8647 LED On/Off Patterns, by State ..................9 Table 3. Configuration Strapping Balls ....................... 10 Table 4. STRAP_RESERVED Ball External Pull-Up/Pull-Down Resistor Requirements ......10 PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 4: Preface
Updated signal names listed in Table 3, and added new October 16, 2007 STRAP_RESERVED table (Table 4). Applied miscellaneous corrections and enhancements. Added STRAP_RESERVED18# and January 9, 2008 STRAP_RESERVED19# to Table 4. PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 5: Introduction
Introduction This quick start hardware design guide is an overview of PLX Technology’s ExpressLane™ PEX 8647 PCI Express Switch and provides examples of how to connect to the various switch interfaces. Switch Interfaces The PEX 8647 device is a 48-Lane, 3-Port Gen 2 switch, designed for graphics systems. Its signal... -
Page 6: Pci Express Link Interface
PCI Express Link. Device 1 Device 2 Channel CDR1 PLL2 Channel CDR2 PLL1 RefClk Figure 1. Sample PCI Express Link Block Diagram PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 7: Transmitter
The standard de-emphasis level is selectable by way of the PEX 8647 Link Control 2 register Selectable De-Emphasis bit (Configuration register, offset 98h[6]). 400mV VTX-DC-CM TXp - TXn 800mV Figure 2. Single-Ended versus Differential Voltage PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... - Page 8 = 750 mV + 162.5 mV = 912.5 mVpp TRANS 750 mV - 162.5 mV = 587.5 mVpp NON-TRANS = 20 log (587.5/912.5) = -3.82 dB TX-DE-RATIO-3.5 DB PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved...
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Page 9: Receiver
Table 1 describes the Receiver equalization effects. Table 1. Receiver Equalization Settings SerDes N Receiver Equalizer[3:0] Equalization 0000b 0010b 0110b Medium 1110b High PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 10: Reference Clock
DC-biasing circuit, and therefore, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors (0603- or 0402-size) to AC-couple the Reference Clock input, as illustrated in Figure PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 11: Channel
Channel length is allowable is to simulate the Channel, using PLX-provided HSPICE models. The PCI Express Base Specification, Revision 2.0, provides additional details for simulating a Channel. PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 12: Jtag Interface
25 MHz, a 15-ohm series terminator can be added to TCK, TDI, and TDO, to improve signal quality. Figure 5 illustrates a generic JTAG interconnection. Figure 5. JTAG Interface Block Diagram PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 13: C Interface
Blinking, 1.5 seconds On, 0.5 seconds Off Link is up, 2.5 GT/s, reduced Lanes are up Blinking, 0.5 seconds On, 1.5 seconds Off PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 14: Strapping Balls
STRAP_RESERVED16 Must be tied directly to Ground (VSS) STRAP_RESERVED17# Must be tied High STRAP_RESERVED18# Must be pulled High STRAP_RESERVED19# Must be pulled High PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 15: Gpio Balls
The recommendation is that 0201-sized capacitors be used in close proximity to these power balls, as illustrated in Figure VDD10 VDD10A 1000 pF 0201 Figure 7. Power Balls and Capacitor Placement PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 16: Power Sequencing
Power supplies isolated through the use of ferrite beads typically have limited access to interplane capacitance, which might have an adverse effect on a given supply rail. 1.7.2 Power Sequencing There is no power sequencing requirement. PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 17: Board-Level De-Coupling
3.3V 2.5V 1.5V 0.0100 1.0V 0.0010 0.0001 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Frequency - Hz Figure 8. Power Plane Impedance versus Frequency PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 18: Figure 9. Capacitor Footprint Effects On Series Inductance
Figure 9 illustrates examples of how various footprints for 0603-size capacitors can change series inductance. Figure 9. Capacitor Footprint Effects on Series Inductance PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 19: Pcb Layout And Layer Stackup Considerations
Figure 7 on page illustrates the placements of 0201 de-coupling capacitors underneath the PEX 8647. PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 20: Figure 10. Top Layer Bga Layout And Routing Escape
Figure 10. Top Layer BGA Layout and Routing Escape Figure 11. Bottom Layer BGA Layout, Escape, and De-coupling Capacitor Placement PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 21: Add-In Board Routing
Differential pairs for PCI Express Gen 2 system boards should have a differential impedance between 68 to 105 ohms (85 ohms, nominal). Figure 13. System Board Routing to PCI Express Slot PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 22: Midbus Routing
Typically, stripline traces are only available for PCBs with six or more layers. Microstrip and stripline traces each have their own properties, which must be weighed when determining which type of trace to use. PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved... -
Page 23: References
PCI Express Card Electromechanical (CEM) Specification, Revision 2.0 Right the First Time: A Practical Handbook on High Speed PCB and System Design, by Lee Ritchie PEX 8647-AA Quick Start Hardware Design Guide, Version 1.2 © 2008 PLX Technology, Inc. All Rights Reserved...
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