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PLX Technology PEX 8680 Hardware Design Manual

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PEX 8680 Quick Start
Hardware Design Guide
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Copyright © 2011 by PLX Technology, Inc. All Rights Reserved – Version 1.1
August 2011
Version 1.1
August 2011
www.plxtech.com
www.plxtech.com/support

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Summary of Contents for PLX Technology PEX 8680

  • Page 1 PEX 8680 Quick Start Hardware Design Guide Version 1.1 August 2011 Website: www.plxtech.com Technical Support: www.plxtech.com/support Copyright © 2011 by PLX Technology, Inc. All Rights Reserved – Version 1.1 August 2011...
  • Page 2 © 2011 PLX Technology, Inc. All Rights Reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.

  • Page 3: Preface

    PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8680, or for any damage or loss caused by deletion of data as a result of malfunction or repair.

  • Page 4: Table Of Contents

    Receiver ............................4 Reference Clock ..........................4 Channel ............................6 PCB Layout and Stackup Considerations ....................6 PEX 8680 BGA Routing Escape and De-Coupling Capacitor Placement ........6 Add-in Board Routing ........................8 System Board Routing ........................8 Midbus Routing ..........................9 PCB Stackup Considerations ......................
  • Page 5 Figure 12. I C Interface Block Diagram ...................... 11 Figure 13. PHPC Circuit Block Diagram ..................... 12 Figure 14. SHPC Interface to PEX 8680 Block Diagram ................13 Figure 15. JTAG Interface Block Diagram ....................14 Tables Table 1. Receiver Equalization Settings ....................... 4 Table 2.
  • Page 6 THIS PAGE INTENTIONALLY LEFT BLANK. PEX 8680 Quick Start Hardware Design Guide, Version 1.1 © 2011 PLX Technology, Inc. All Rights Reserved.

  • Page 7: Introduction

    PCI Express Switches and provides examples of how to connect to the various switch interfaces. PCI Express Link Interface PLX’s PEX 8680 is an 80-Lane, 20-Port PCI Express 2.0 (that is, Gen2)-compliant switch. PCI Express 2.0 supports transfer rates of 5.0 GT/s per Lane. The Physical Media Attachment (PMA) Layer for each Lane is implemented as a SerDes transceiver, which is composed of a transmit path and receive path.

  • Page 8: Transmitter

    Set their de-emphasis level, accordingly. Longer Links should use 6.0 dB, whereas shorter Links can use the 3.5 dB level. The standard de-emphasis level is selectable by way of the PEX 8680 Link Control 2 register Selectable De-Emphasis bit (Configuration register, offset 98h[6]).
  • Page 9 In addition to supporting the standard de-emphasis levels, the PEX 8680 has a number of programmable registers to control the Transmitter’s characteristics, such as drive level and de-emphasis. The SerDes Transmitter Control registers exist in Station Ports 0, 4, 8,16, and 20 each controlling a bank of 16 SerDes (Lanes [0-15], [16-31], [32-47], [64-79], and [80-96] respectively).

  • Page 10: Receiver

    Receiver equalization only needs to be used on longer channels. The PEX 8680 provides a programmable receive equalization function. Ports 0, 4, 8, 16, and 20 each have a set of Receiver Equalizer registers, located at offsets 0xBA4h and 0xBA8h, to control a group of 16 SerDes.

  • Page 11: Figure 3. Transport Delay Delta

    Reference Clock transport delay delta. The PEX 8680 PEX_REFCLKn/p signal is the Reference Clock Input buffer. It has an internal DC-biasing circuit, and hence, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors...

  • Page 12: Channel

    “dog-bone” nets from the pad to a via which will connect it with an internal power or ground plane. The PEX 8680 places all Transmitter differential pairs on the outer two rows of balls and Receiver differential pairs on rows four and five. This means only two signal layers are required in a PCB stackup to escape the differential pairs from the BGA.

  • Page 13: Figure 5. Top Layer Bga Layout And Routing Escape

    Figure 5. Top Layer BGA Layout and Routing Escape Figure 6. Bottom Layer BGA Layout, Escape, and De-coupling Capacitor Placement PEX 8680 Quick Start Hardware Design Guide, Version 1.1 © 2011 PLX Technology, Inc. All Rights Reserved.

  • Page 14: Add-In Board Routing

    Add-in Board Routing Although the PEX 8680 Transmitter pairs escape on the top layer (as previously mentioned), at some point they must route to the bottom layer to connect to the gold fingers as is the case for an add-in board.

  • Page 15: Midbus Routing

    Typically, stripline traces are only available for PCBs with six or more layers. Microstrip and stripline traces each have their own properties, which must be weighed when determining which type of trace to use. PEX 8680 Quick Start Hardware Design Guide, Version 1.1 © 2011 PLX Technology, Inc. All Rights Reserved.

  • Page 16: Non-Transparent Function

    3 Non-Transparent Function The PEX 8680 supports Non-Transparent (NT) function. There are three ways to enable the NT function and configure the NT Port for the PEX 8680. Method 1. Use of the Strapping balls:  STRAP_NT_ENABLE#  STRAP_NT_UPSTREAM_PORTSEL[4:0] Pull down the STRAP_NT_ENABLE# to logic zero (0) to enable the NT function. Pull up or down the STRAP_NT_UPSTREAM_PORTSEL[4:0] to select the NT Port.

  • Page 17: C Interface

    C Interface Block Diagram Hot Plug Circuitry The PEX 8680 supports four Parallel Hot Plug Controllers (PHPC) and up to nineteen Serial Hot Plug Controllers (SHPC), to service its downstream Ports. The PHPCs are designated as Hot Plug Ports A, B, C, and D.

  • Page 18: Figure 13. Phpc Circuit Block Diagram

    PEX 8680 must be Set, and boot with serial EEPROM is essential. After the PEX 8680 is powered up, the state machine inside the PEX 8680 scans the number of I/O expander ICs connecting to the I C Bus, starting from Address 000h, in ascending order.

  • Page 19: Jtag Interface

    IO 6 GPIO AD[2:0] MAX7311 or PCA9698 Figure 14. SHPC Interface to PEX 8680 Block Diagram JTAG Interface The PEX 8680 supports a five-ball JTAG Boundary Scan interface. The JTAG interface consists of the following signals:  JTAG_TCK  JTAG_TMS ...

  • Page 20: Pci Express Port Good Indicators

    PEX_PORT_GOOD[23:16,11:0]#. These Output balls can be used to build the Port Status LED circuits, to indicate the status of each PEX 8680 Port. Each Port has five states, which are related to Link Status, Channel Speed, and the Port’s Lane width.

  • Page 21: Table 3. Cross-Reference Of Ball Names And Related Debug Signal Names

    HP_PWRLED_B# prb_outB6 rcvr_dat6 HP_PERST_B# prb_outB5 rcvr_dat5 HP_CLKEN_B# prb_outB4 rcvr_dat4 GPIO7 prb_outB3 rcvr_dat3 GPIO6 prb_outB2 rcvr_dat2 GPIO5 prb_outB1 rcvr_dat1 GPIO4 prb_outB0 rcvr_dat0 PEX 8680 Quick Start Hardware Design Guide, Version 1.1 © 2011 PLX Technology, Inc. All Rights Reserved.
  • Page 22 NC_on_W9 PROCMON rclk/2 SPARE1 ext_trig_in SPARE2 trig_out trig_out PEX_PORT_GOOD12# xmit_dat19 GPIO1 xmit_dat18 GPIO8 rcvr_dat18 GPIO9 rcvr_dat19 GPIO10 rx_sts0 GPIO11 rx_sts1 GPIO12 rx_sts2 PEX 8680 Quick Start Hardware Design Guide, Version 1.1 © 2011 PLX Technology, Inc. All Rights Reserved.

  • Page 23: Pex 8680 Configuration Strapping Balls

    PEX 8680 Configuration Strapping Balls The PEX 8680 has a total of 47 Strapping balls. Twenty-six of them service different configuration functions (STRAP_NT_ENABLE#, STRAP_NT_UPSTRM_PORTSEL[4:0], STRAP_UPSTRM_PORTSEL[4:0], STRAP_STNx_PORTCFG[1:0] for each of the six Stations, and STRAP_VS_MODE[2:0]). For the PEX 8680, internal pull-up and pull-down resistors set the default configuration.

  • Page 24: Gpio Balls

    GPIO Balls The PEX 8680 has 43 GPIO balls – 23 are dedicated GPIO balls, and 20 share GPIO and PEX_PORT_GOOD[23:16,11:0]# functions in standard operation. Depending on the settings of the Test mode balls, STRAP_TESTMODE[4:0], the GPIO balls can be set as input or output. If Serial Hot Plug is...

  • Page 25: Power Supplies

    11.1 Power Supplies The PEX 8680 has the following Power ball groups:  VDD10 – Digital core logic supply  VDD10A – SerDes analog supply  VDD25 – Hot Plug, serial EEPROM, I C, JTAG, Port Status indicators, I/O buffers ...
  • Page 26 If a PCB layer stackup is such that plane capacitors are not possible, add power or ground fill areas on the signal layers, as follows: PEX 8680 Quick Start Hardware Design Guide, Version 1.1 © 2011 PLX Technology, Inc. All Rights Reserved.
  • Page 27 50 mil 50 mil 0603 (780 pH) 0603 (580 pH) 150 mil 0603 (1,190 pH) Figure 17, Capacitor Footprint Effects on Series Inductance PEX 8680 Quick Start Hardware Design Guide, Version 1.1 © 2011 PLX Technology, Inc. All Rights Reserved.

  • Page 28: References

    PCI Express Card Electromechanical (CEM) Specification, Revisions 1.0a and 1.1  Right the First Time: A Practical Handbook on High Speed PCB and System Design, by Lee Ritchie PEX 8680 Quick Start Hardware Design Guide, Version 1.1 © 2011 PLX Technology, Inc. All Rights Reserved.

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