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U16 ZR36732PQC PINS DESCRIPTION - CONTINUED
Pin No.
Pin Name
Type
General Purpose I/O (Host Interface)
134
GPAIO
3-S
General purpose input/output pin,monitored/controlled by the audio processor
software.After RESET, this pin is defined as input.Its definition can be configured
through ADP commands.
145
GPSI
I
General purpose input,monitored by the system de-multiplexer/video processor
software.
143
GPSO
O
General purpose output,controlled by the system de-multiplexer/video processor
software. After RESET it outputs a low level.
DVD-DSP interface
151
DVDREQ
O
DVD-DSP data request output (programmable polarity)
149
DVDVALID
I
DVD-DSP data valid input (programmable polarity)
148
DVDSOS
I
DVD-DSP start of sector input (programmable polarity)
159,158
DVDAT[7],[6]
I
DVD-DSP data input bus.
157,156
DVDAT[5],[4]
155,154
DVDAT[3],[2]
153,152
DVDAT[1],[0]
150
DVDSTRB
I
DVD-DSP data bit strobe (clock)input. Programmable polarity.
147
DVDERR
I
DVD-DSP error indication input.Programmable polarity.
5
CDERR
I
When HWID is connected to GNDP, these are the CD DSPI
6
CDFRM
CDERR: data error indication input
7
CDDAT
CDFRM: Ieft/right channel frame input
8
CDCLK
CDDAT: data input
CDCLK:bit clock input
When HWID is connected to VDDP, these are HD [15:12] of the host data bus ,as
explained in the host interface pin description.
Video Syncs and Clocks Interface
127
VCLKx2
3-S
Main video clock.27.000MHz.
92
VCLK
3-S
A division by two of the VCLKx2 signal. This signal is used as a sync qualifier.
95
HSYNC
3-S
Horizontal sync. Polarity and duration are programmable.
93
VSYNC
3-S
Vertical sync. Polarity and duration are programmable.
96
FI
3-S
Field indication. Polarity is programmable.
Analog Video Encoder Interface
102
CVBS/G/Y
O
When the Decoder outputs composite video, this line is CVBS
(DAC A)
When the Decoder outputs RGB, this line is the Green output
When the Decoder outputs YUV,this line is the Y output
105
Y/R/V
O
When the Decoder outputs the composite video,this line is Y
(DAC B)
When the Decoder outputs RGB, this line is the Red output
When the Decoder outputs YUV,this line is the V output
106
C/B/U
O
When the Decoder outputs the composite video,this line is C
(DAC C)
When the Decoder outputs RGB,this line is the Blue output
When the Decoder outputs YUV,this line is the U output
103
CVBS/C
O
When the Decoder outputs any of the types of video,this line can be programmed to
(DAC D)
output either composite or C.
108
RSET
I
Resistive load for gain adjustment of the DACs
111
VREF
I
Voltage reference for gain adjustment of the DACs
100
COSYNC
3-S
Composite sync output,Active only when RGB analog output is selected. Otherwise,
the signal is low.
Digital Audio Interface
131
AMCLK
3-S
Audio Master Clock input/output.128,192,256 or 384 times the sampling frequency
(programmable)
133
S/PDIF
O
S/PDIF transmitter output for digital coded or reconstructed audio data. Alternately
(AOUT[3])
can be used as a fourth audio output. After RESET this pin outputs low level.
138,137
AOUT[2],[1]
O
Serial outputs of digital stereo audio.
136
AOUT[0]
Description
2
S input port pins as follows:
75
U16 ZR36732PQC PINS DESCRIPTION - CONTINUED
Pin No.
Pin Name
Type
113
AIN
I
Serial input of digital stereo audio.
139
ALRCLK
O
Digital audio left/right select output for the audio port. Square wave,at the sampling
frequency.Programmable polarity interpretation for input.
141
ABCLK
O
Digital audio bit-clock output. Data on AOUT and AIN is output or latched, respectively,
with the rising or falling (programmable)edge of this clock.
PLL/Clock Interface
120
GCLK
I
27.000MHz clock or crystal input for main processing clock generation.
117
GCLK1
I
27.000MHz clock input for audio master clock generation.in normal operation must be
connected to GCLK.
119
XO
O
Output to a crystal that is connected to GCLK. If a crystal is not used at GCLK, XO
must be left not connected.
115
PLLCFG[1]
I
PLL configuration inputs. Allowed to be changed only during RESET. In normal
118
PLLCFG[0]
operation both pins must be connected to GNDP
SDRAM Interface
90,87
RAMDAT[15],
3-S
SDRAM bidirectional data bus.
84,81
[14],[13],[12]
78,75
RAMDAT[11]
72,68
[10],[9],[8]
70,74
RAMDAT[7],[6]
76,79
RAMDAT[5],[4]
82,85
RAMDAT[3],[2]
88,91
RAMDAT[1],[0]
55,53
RAMADD[11]
O
SDRAM address bus output.
54,51
[10],[9],[8]
48,46
RAMADD[7],[6]
43,41
RAMADD[5],[4]
42,45
RAMADD[3],[2]
47,50
RAMADD[1],[0]
60
RAMRAS#
O
SDRAM row select output.
61
RAMCAS#
O
SDRAM column select output.
66
PCLK
O
SDRAM clock output (Same as internal processing clock)
64
RAMDQM
O
SDRAM data masking output.
57
RAMCS0#
O
SDRAM chip select output for the lower (or only) 2MB device (16Mbit)
59
RAMCS1#
O
SDRAM chip select output for the upper 2MB device (16Mbit).
62
RAMWE#
O
SDRAM write enable output.
Test Signal Interface
125
SCNENBL
I
Production test pin (connected directly to GNDP in normal operation).
129
TESTMODE
I
In normal operation this pin must be connected directly to GNDP.
112
ICEMODE#
I
In normal operation this pin must be connected directly to VDDP.If it is asserted, then the
ADP goes into ICE mode. In this mode 4 of the Decoder pins turn into ICE interface pins:
HD[11] = TCK - ICE interface clock
HD[10] = TMS -ICE interface mode select input
HD[9] = TDO -ICE interface data output
HD[8] = TDI - ICE interface data input
Power Signals
10,40,49
GNDP
Digital ground of 3.3 V supply.
56,64,69
80,86,97
128,146
3,16,19,26
V
3.3V Digital power supply.
DDP
38,44,52,58
67,71,77,83
89,94,98,99
126,135,140
Description
76
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