Lvds Display Interface - Onkyo TX-SR606 Service Manual

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-26
Q8001 : FLI30502 (LCD TV Controller with Worldwide Standard Sound Processor
and HDMI Receiver)-8/12
TERMINAL DESCRIPTION

LVDS Display interface

Pin Name
PBIAS
PPWR
AVDD_LV_33
AVSS_LV
CH3P_LV_E
CH3N_LV_E
CLKP_LV_E
CLKN_LV_E
CH2P_LV_E
CH2N_LV_E
CH1P_LV_E
CH1N_LV_E
CH0P_LV_E
CH0N_LV_E
VSS_OUT_LV
VDD_OUT_LV_33
CH3P_LV_O
CH3N_LV_O
CLKP_LV_O
CLKN_LV_O
CH2P_LV_O
CH2N_LV_O
CH1P_LV_O
CH1N_LV_O
CH0P_LV_O
CH0N_LV_O
AVSS_OUT_LV
AVDD_OUT_LV_33
Pin # I/O Description
O
71 Panel Bias Control (backlight enable, tri-state output, 5 V tolerant).
O
72 Panel Power Control (tri-state output, 5 V tolerant).
DP
74 Digital Power for LVDS Block. Connect to digital 3.3V supply.
73 G Ground for LVDS outputs.
75 O These form the Differential Data Output for Channel 3 (Even).
76 O
O
77 These form the Differential Clock Output Even Channel.
O
78
O
79 These form the Differential Data Output for Channel 2 (Even).
O
80
81 O These form the Differential Data Output for Channel 1 (Even).
82 O
83 O These form the Differential Data Output for Channel 0 (Even).
O
84
G
85 Ground for LVDS outputs.
DP
86 Digital Power for LVDS outputs. Connect to digital 3.3 V supply.
O
87 These form the Differential Data Output for Channel 3 (Odd).
88 O
89 O These form the Differential Clock Output Odd Channel.
90 O
O
91 These form the Differential Data Output for Channel 2 (Odd).
O
92
O
93 These form the Differential Data Output for Channel 1 (Odd).
94 O
95 O These form the Differential Data Output for Channel 0 (Odd).
96 O
G
97 Ground for LVDS outputs.
DP
98 Digital Power for LVDS outputs. Connect to digital 3.3 V supply.
TX-SR606