Onkyo TX-SR606 Service Manual page 56

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-23
Q8001 : FLI30502 (LCD TV Controller with Worldwide Standard Sound Processor
and HDMI Receiver)-5/12
TERMINAL DESCRIPTION
Low bandwidth ADC input port
Pin Name Pin #
VDDA33_LBADC 1
LBADC_IN1 2
LBADC_IN2 3
LBADC_IN3 4
LBADC_IN4 5
LBADC_IN5 6
VSSA3_LBADC 7
RCLK PLL Pins
Pin Name Pin #
VBUFC_RPLL 9
VDD_RPLL_18 10
GND_RPLL_18 11
XTAL 12
TCLK 13
AVDD_RPLL_33 14
Digital video Input port
Pin Name Pin #
VID_CLK_1 151
VIDIN_HS 53
VIDIN_VS 54
VID_DATA_IN_0 141
VID_DATA_IN_1 142
VID_DATA_IN_2 145
VID_DATA_IN_3 146
VID_DATA_IN_4 147
VID_DATA_IN_5 148
VID_DATA_IN_6 149
VID_DATA_IN_7 150
VID_DATA_IN_8 162
VID_DATA_IN_9 163
VID_DATA_IN_10 165
VID_DATA_IN_11 166
VID_DATA_IN_12 170
VID_DATA_IN_13 171
VID_DATA_IN_14 173
VID_DATA_IN_15 174
I/O Description
AP Analog Powet (3.3V) for Low Bandwidth ADC Block. Must be bypassed with a 0.1 uF capacitor.
AI Low Bandwidth Analog input 1. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
AI Low Bandwidth Analog input 2. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
AI Low Bandwidth Analog input 3. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
AI Low Bandwidth Analog input 4. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
AI Low Bandwidth Analog input 5. The input signal connected to this pin, must be bypassed with a
0.1 uF capacitor and could be in the range of 0 to 3.3V. (peak to peak)
AG This pin provides the Return Path for LBADC inputs. Must be directly connected to the analog
system ground plane on board.
I/O Description
O Test Output. Leave this pin open. This reserved for factory testing purpose.
DP Digital power (1.8V) for ADC digital logic. Must be bypassed with capacitor to ground plane.
DG Digital GND for ADC clocking circuit. Must be directly connected to the digital system ground
plane.
AO Crystal oscillator output. Connect to external crystal.
AI Reference clock (TCLK) from the 19.6608 MHz crystal oscillator. Connect to external crystal
oscillator.
AP Analog Power (3.3V) for RCLK PLL. Must be byppased with a 0.1 uF capacitor.
I/O Description
I Video port data clock input meant for Video Input 1. Up to 135 MHz (Input, 5 V tolerant).
I When Video Input 1 is in BT656 mode, this pin acts as HSync Input for Video Input 2;
I When Video Input 1 is in BT656 mode, this pin acts as VSync Input for Video Input 2;
IO Input YUV data in 8-bit BT656 of Video Input 1
(Bidirectional, 5 V tolerant); or Y[0:7] in 16-bit format or Y/G[0:7] in 24-bit mormat
IO Input C [0:7] data in 16-bit fomat OR B/U in 24-bit format
TX-SR606