Cherry Theobroma PX30-mQ7 User Manual page 44

11.3.4 I2C
Q7 Signal Type
Q7_I2C_CLK O
Q7_I2C_DAT I/O
LVDS_DID_CLK O
/GP2_I2C_CLK
LVDS_DID_DAT I/O
/GP2_I2C_DAT
LVDS_BLC_DAT O
LVDS_BLC_CLK I/O
11.3.5 I2S
Q7 Signal Type
I2S_RST# O
I2S_WS O
I2S_CLK O
I2S_SDO O
I2S_SDI I
11.3.6 Video
The Q7 LVDS_A pins support LVDS and MIDI-DSI. LVDS and MIPI-DSI signals are electrically compatible in the sense that
nothing will be damaged, but are not defined in the Qseven standard.
The MIPI-DSI specifications are:
• MIPI DSI D-PHY v1.0
• Up to four data lates
• Up to 1.0 Gbps per lane
The signal mapping is shown below:
The Q7 LVDS_B pins are used as MIPI-CSI. The specifications are:
• MIPI CSI D-PHY v1.0
• Up to four data lanes
• Up to 1.0 Gbps per lane
The signal mapping is shown below:
v1.2.0-1-g5ccabb6
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Signal Description
Level
3.3V I2C bus clock line connected to PX30
3.3V I2C bus data line connected to PX30
3.3V I2C bus clock line connected to PX30, Secure Element, STM32, Attiny
and Video connector
3.3V I2C bus data line connected to PX30, Secure Element, STM32, Attiny
and Video connector
3.3V I2C bus clock line connected to PX30, Video connector and baseboard
EEPROM
3.3V I2C bus data line connected to PX30, Video connector and baseboard
EEPROM
Signal Description
Level
3.3V I2S Codec Reset
3.3V I2S Word Select
3.3V I2S Serial Data Clock
3.3V I2S Serial Data Output
3.3V I2S Serial Data Input
Q7 Signal Function 1
LVDS_A0_P LVDS_A0+
LVDS_A0_N LVDS_A0-
LVDS_A1_P LVDS_A0+
LVDS_A1_N LVDS_A1-
LVDS_A2_P LVDS_A2+
LVDS_A2_N LVDS_A2-
LVDS_A3_P LVDS_A3+
LVDS_A3_N LVDS_A3-
LVDS_A_CLK_P LVDS_A_CLK+
LVDS_A_CLK_N LVDS_A_CLK-
Function 2
DSI_D0+
DSI_D0-
DSI_D1+
DSI_D1-
DSI_D2+
DSI_D2-
DSI_D3+
DSI_D3-
DSI_CLK+
DSI_CLK-