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(3) Horizontal transfer clock waveform
tr
Hφ
2β
90%
10%
Hφ
1β
Cross-point voltage for the Hφ
The overlap period for twh and twl of horizontal transfer clocks Hφ
(4) Reset gate clock waveform
tr
RG waveform
V
RGLH
V
RGLL
V
RGLm
V
is the maximum value and V
RGLH
Point A in the above diagram until the rising edge of RG.
In addition, V
is the average value of V
RGL
V
= (V
+ V
RGL
RGLH
Assuming V
is the minimum value during the interval twh, then:
RGH
Vφ
= V
– V
RG
RGH
Negative overshoot level during the falling edge of RG is V
(5) Substrate clock waveform
(Internally generated bias)
twh
Vφ
H
two
rising side of the horizontal transfer clocks Hφ
1β
twh
tf
Vφ
RG
is the minimum value of the coupling waveform during the period from
RGLL
RGLH
)/2
RGLL
RGL
100%
90%
10%
V
0%
SUB
tf
Vφ
H
2
and Hφ
1β
V
RGH
twl
Point A
and V
.
RGLL
.
RGLm
Vφ
SUB
tr
twh
tf
– 9 –
V
CR
twl
V
HL
and Hφ
waveforms is V
1β
2β
is two. (
β = A, B
)
2β
φM
φM
2
ICX274AL
.
CR
V
RGL
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