Block Diagram (Logical) - Siemens SIMATIC S7-1500 Manual

Wiring

4.3 Block diagram (logical)

4.3 Block diagram (logical)
Symbolic structure and function of the TM NPU
The figure below shows the symbolic structure, method of operation and software
architecture of the TM NPU:
Hardware Accelerator Intel® Movidius™ Myriad™ X Vision Processing Unit (VPU)
The core operations of the TM NPU are performed by the Intel® Movidius™ Myriad™ X VPU
processor. The processor has a Neural Compute Engine: a specially developed hardware
accelerator for deep learning inferences in neural networks.
The Neural Compute Engine in conjunction with the 16 powerful SHAVE cores and high-
throughput intelligent memory structure makes Intel® Movidius™ Myriad™ X ideal for on-
device deep neural networks and computer vision applications.
The OpenVINO™ toolkit is used to prepare neural networks for the Myriad X.
Reference: Intel Movidius (https://www.intel.com/)
24
Technology Module TM NPU
Equipment Manual, 07/2023, A5E46384784-AC