Nand, Sata Interface, Ethernet Circuit Diagram - LG BD390 Service Manual

4. NAND, SATA INTERFACE, ETHERNET CIRCUIT DIAGRAM

SLC NAND : 1GB
IC402
NAND08GW3B2C(TSOP-48)
EBI_DATA[0-7]
2:G5 EBI_DATA[0] 29 I/O0
EBI_DATA[1] 30 I/O1
31 I/O2
EBI_DATA[2]
EBI_DATA[3] 32 I/O3
EBI_DATA[4] 41 I/O4
EBI_DATA[5] 42 I/O5
EBI_DATA[6] 43 I/O6
VCC_3V3
44
EBI_DATA[7] I/O7
VCC_3V3
R451 0 19 WP
R487 R488
16 CLE
2:F2;5:H6 NAND_CLE
OPEN 10k
17 ALE
2:F2;5:H6 NAND_ALE
15 NC
TP439
14
NC
TP440
10 NC
2:F3 EBI_nCS1
9 CE
2:F3 EBI_nCS0 8
RE
2:F2;5:H6 NAND_nRE
18 WE
2:F3;5:H6 EBI_nWE0
TP437
TP436 VCC_3V3
4 NC
TP438
R486 5 NC
1k 6 NC
7
R/B
2:F3 EBI_NAND_RB
38 NC
USB I/F
VCC_3V3
TP401
TP443 R481
USB0_PWRON R496
5:F5;5:H6
5:F5 USB1_PWRON
10K 10K
5:F5 USB0_PWRFLT
USB1_PWRFLT
5:F5
JIG422
R472 0
5:F5
USB1_DN
R473 0
5:F5
USB1_DP
JIG423
R485 0
5:F5 USB0_DN
0
R484
5:F5 USB0_DP
WiFi I/F
D402
SRV05-4
VCC_5V_LOADER
JIG454
1 6
2 5
3 4
DGND
CN409
1 USB_5V
C5 2
USB0_D- D-
C5 USB0_D+ 3 D+
4 GND
DGND
IC403
OPEN_NC7SZ125M5X
1 OE
2 A
5:F5;6:B5 AUD_FS_CLK0
3 GND
DGND
R490
VCC_3V3
VCC 37
VCC 12
C433 C445 C432 CA410
0.1uF 0.1uF 1uF 100uF/6.3V
VSS 36
VSS 13
DGND
NC 48
NC 47
NC 46
NC 45
NC 40
NC 39
NC 35
NC 34
NC 33
NC 28
NC 27
NC 26
25
NC
NC 24
NC 23
NC 22 JIG421
NC 21 JIG412
NC 20 JIG413
NC 11
JIG414
NC 3
NC 2
JIG415
NC 1
JIG416
JIG417
JIG418
JIG419
JIG420
DGND
5:C4
5:C4
*USB Design & Layout Guide*
1.USB Data DP/DN must be routed as 100ohm differential pairs.
2.Match Trace length of DP/DN
3.Trace spacing is same as trace width.
4.Route differential pairs above gnd plane and gnd plane are not split under differential pairs.
5.Avoid via aspossible as you can.
6.Trace spacing between DP/DN and other traces must be more than 5 times of DP/DN trace width.
7.Consider current upto 500mA.
8.Consider abrupt USB power short.
C447
I3
USB1_D- DGND
USB1_D+ I3
SGPIO00/BSC_M0_SCL
5:F4;5:G3
SGPIO01/BSC_M0_SDA
5:F3;5:G2
USB0_D- A7
USB0_D+ A7
7.1CH AUDIO INTERFACE
5:F4 UART_TX3
UART_RX3
5:F4
TP402
TP403
CN404
JIG435
5V_BSC_M0_SDA 1 SDA
G5
JIG436
5V_BSC_M0_SCL 2 SCL
G5
3 GND
R467 33 JIG437
4 FS_CLK_0
JIG438
5:C5 I2S_CLK 5 I2S_SCK
JIG439
5:C5 6 I2S_LRCK
I2S_LRCLK
GND
7
JIG440
5:C5 I2S_DATA0 8 I2S_DATA0
JIG441
5:C5 I2S_DATA1 9 I2S_DATA1
JIG442
5:C5;5:H6 10 I2S_DATA2
I2S_DATA2
JIG443
5:C5;5:H6 11 I2S_DATA3
I2S_DATA3
JIG444
J4;6:B3 MICOM_AUD_MUTE 12 AUDIO_MUTE
VCC_12V_AUDIO
13 GND
VCC_3V3
JIG445
14 12V_AUDIO
DGND 0.1uF
C450
5 15 GND
VCC
VCC_5V_AV JIG446
16 5V_AV
DGND 0.1uF C451
JIG455
Y 4 17 RESET_8CHDAC
RESET_8CHDAC
18 5.3VA
JIG447
F8
19 IR
5:F4 IR_TX
DGND 20 GND
VCC_5.6V_L
0
VCC_3V3
DGND
C448 0.1uF
0.1uF
C452 R497
2SK3018 R492
4.7K
Q405
DGND
RESET_AUDIO_CARD/GPIO_12
5:F3
*SATA Design & Layout Guide*
1.SATA Data DP/DN must be routed as 100ohm differential pairs.
2.Match Trace length of DP/DN
3.Trace spacing is same as trace width.
4.Route differential pairs above gnd plane and gnd plane are not split under differential pairs.
5.Avoid via aspossible as you can.
6.Trace spacing between DP/DN and other traces must be more than 5 times of DP/DN trace width.
7.SATA Xstal(X102) must be place close to BCM7440.
8.Trace Length must be less than 100mm.
9.Place ac-coupling capacitor(C405,411,402,419) close to Connector
VCC_12V_LOADER
VCC_5V_LOADER
CA416
C430
CN405
100UF/16V
0.1uF INST_OPEN
1
DGND DGND
12V_LOADER
2
GND
3
GND
4
CA417
C429
5 5V_LOADER
100UF/16V
0.1uF
I5
DGND DGND INST_OPEN
DGND
BBS I/F
VCC_3V3
CN401
R436 R433
1.2k 1.2k
DGND
BSC_S_SDA TP408
BSC_S_SCL TP404
VCC_3V3
CA401
C409
22uF/16V
0.1uF
DGND
VCC_5V_AV
VCC_3V3
0.1uF
2SK3018 R495 R494
2K
Q404 2K
5V_BSC_M0_SCL
5V_BSC_M0_SDA
2SK3018
Q403
VCC_3V3 VCC_5.6V_L
C408 0.1uF
R437 2SK3018 R439 R438
R440
10K
OPEN 10K Q401 10K
DGND
JIG401
UART_TXD_3 K4
JIG405
UART_RXD_3 K4
2SK3018
Q406
DEBUGGING CONSOLE (UART1)
VCC_5V_AV
VCC_3V3
TP409
JIG431
CA404
TP412
R454 22uF/16V
4.7k
DGND
L406
HB1608_1000
5:F4 UART_RX0
L407
HB1608_1000
5:F4;5:H6 UART_TX0
VCC_3V3
JIG432
R476
OPEN_47k
5:F3 GPIO_19_UART_PROTECTION
R475
47k
VCC_3V3
TP442 TP414
R489 DGND
VCC_5V_AV TP441 TP413
4.7k
5:F4 UART_RX1 5:F4 UART_RX2
10K
5:F4;5:H6 UART_TX1 5:F4;5:H6 UART_TX2
RESET_8CHDAC
3-83 3-84
LOADER SATA INTERFACE
*IMPEDANCE MATCHING IS REQUIRED : 100 OHM (AT EACH DIFFERENTIAL LINE)
*TRACE LENGTH MUST BE LESS THAN 100mm
CN406
DGND
1
C405 10nF
5:F5 SATA_TXDP1 2 SATA_TXDP1
C411 10nF
5:F5 SATA_TXDN1 3 SATA_TXDN1
4 DGND
C402 10nF
SATA_RXDN1
5:F5 SATA_RXDN1 5
C419 10nF
SATA_RXDP1
5:F5 SATA_RXDP1 6
7 DGND
JIG408
JIG403
DGND
JIG404
JIG402
D400
SRV05-4_OPEN
VCC_5V_LOADER
1 6
5 FRONT PANEL I/F
2
3 4
H6 IR_TX
DGND
C5 USB1_D+
C4 USB1_D-
JIG409
P_CON_1V8
JIG448
7:D3;7:H3
VCC_5.6V_L
JIG452
FD-
JIG406
H6 UART_RXD_3
UART_TXD_3
H6
JIG453
FD+
JIG407
HDMI_CEC_CON
VCC_5.6V_L 6:I5
MICOM_AUD_MUTE
R480 D7;6:B3
R498 4.7K
JIG449
47K
DGND
JIG450 P_CON_3V3_LOADER 7:B3;7:F5
INST_OPEN
H2
P_CON_1V2
7:D4
C449 JIG451
VCC_5V_LOADER
OPEN(0.1uF) -29VA
JIG410
DGND
C443 CA415
0.1uF
100UF/16V
DGND
JIG411
DGND
ETHERNET
VCC_2V5
L405 HB2012_1000
CA407 RB1-105B82KA
C427
22uF/16V
0.1uF JK403
DGND DGND
1 TD+
5:F4 EPHY_TDP
2 TD-
5:F4
EPHY_TDN
3 RD+
5:F4
EPHY_RDP
C425
JIG426
4 TCT
DGND
5 RCT
1000pF
6 RD-
5:F4 EPHY_RDN
7 NC
8 GND
L408
9 NC
HB1608_1000
10 NC
JIG433
C417
0.1uF
CN403
DGND
RX
1
2 TX
3 PROTECT JIG430
4 NC
5V
5
*IMPEDANCE MATCHING IS REQUIRED : 100 OHM (AT EACH DIFFERENTIAL LINE)
JIG434
6 GND
*Ethernet Design & Layout Guide*
1.Eth Data DP/DN must be routed as 100ohm differential pairs.
DGND
2.Match Trace length of DP/DN
3.Trace spacing is same as trace width.
4.Route differential pairs above gnd plane and gnd plane are not split under differential pairs.
VCC_3V3 5.Avoid via aspossible as you can.
6.Trace spacing between DP/DN and other traces must be more than 5 times of DP/DN trace width.
R455
4.7k
25 IR
24 GND
23 GND
22 USB_D+
21 USB_D-
20 GND
19 PWR_CTRL_5.3V
18 5.3VA
FD-
17
16 GND
15 UART_RX3
14 UART_TX3
13 FD+
12 GND
11 HDMI_CEC
10 MICOM_AUD_MUTE
9 PWR_CTRL
8 INST_OPEN
D2
7
6 D3
5 nRESET
4 D1
3 -29VA
2 USB_5V
1 USB_5V
CN408
TOP VIEW
2 4 6 8
1 3 5 7
9 10
2009.2.16
4.NAND,SATA
INTERFACE,ETHERNET