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• Note for Printed Wiring Boards and Schematic Diagrams
Note on Printed Wiring Boards.
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
•
a
: Through hole.
•
f
: internal component
•
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side:
Parts on the pattern face side seen from
(Side B)
the pattern face are indicated.
Parts face side:
Parts on the parts face side seen from
(Side A)
the parts face are indicated.
• Waveforms
1
IC704 qc ( X IN )
2
IC806 2 ( A )
1.6 Vp-p
5 MHz
49.152 MHz
0.5 V/DIV, 0.1 µ sec/DIV
0.1 V/DIV, 50 µ sec/DIV
• IC Block Diagrams
IC801 CS8416-CZZR
4:2
MUX
AES3 RX
&
DECODER
SA-iP001P
SECTION 2
DIAGRAMS
Note on Schematic Diagrams.
• All capacitors are in µF unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ω and
1
/
W or less unless otherwise
4
specified.
•
f
: internal tolerance.
• C : panel designation.
Note:
Note:
The components identi-
Les composants identifiés
par une marque 0 sont cri-
fied by mark 0 or dot-
ted line with mark 0 are
tiques pour la sécurité.
Ne les remplacer que par une
critical for safety.
Replace only with part
piéce portant le numéro
number specified.
spécifié.
• A : B+ Line.
• Voltages are dc with respect to ground under no-signal
conditions.
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Signal path.
F
: AUDIO
0.5 Vp-p
IC803 CXD9774M
GND 1
PWM BP 2
GND 3
RESET 4
DREG RTN 5
SERIAL
AUDIO
GVDD 6
OUTPUT
DE–EMPHASIS
M3 7
FILTER
DREG 8
DGND 9
M1 10
M2 11
DVDD 12
SD 13
DGND 14
OTW 15
GND 16
PWM AP 17
GND 18
IC802 CXD9788AR
PWM
1
2
3
4
5
GVDD
DVDD DREG
DREG
OCH
PWM
GATE
RECEIVER
DRIVE
TIMING
CONTROL
DGND
&
PROTECTION
GATE
DRIVE
OCL
DIGITAL
DREG
REGULATOR
GVDD
DREG
PROTECTION
LOGIC
OT
OCL
&
UVP
GATE
DRIVE
TIMING
CONTROL
DVDD DREG
&
PROTECTION
PWM
GATE
RECEIVER
DRIVE
DGND
DREG
OCH
GVDD
3
3
48
47
46
45
44
43
42
41 40 39 38 37
Filter
Liner
∆ ∑ Converter
&
Gain
Interpolator
LOW
Control
CUT
Filter
Clock Generator
(Secondary Clock System)
INIT/MUTE
Serial Control
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
IC901 MR4010-7103
VCC
4
36
GVDD B
35
GVDD B
LATCH CIRCUIT RESET
UVLO
34
GND
COMPARATOR
COMPARATOR
–
33
BST B
+
OVP
COMPARATOR
VUL
32
PVDD B
–
31
PVDD B
+
30
OUT B
R
29
OUT B
VOVP
Q
THERMAL
S
28
GND
SHUTDOWN
CIRCUIT
ZERO CURRENT
Z/C
1
DETECTION CIRCUIT
TURN–ON
DEAD TIMER
STANDBY
CIRCUIT
27
GND
VREF
26
OUT A
IF/B
25
OUT A
F/B
2
24
PVDD A
–
23
PVDD A
ON WIDTH
+
TIMER
3
22
BST A
GND
21
GND
20
GVDD A
19
GVDD A
SA-iP001P
Sampling Rate
Converter
DF2
DF1
S
P
36
XFSIIN
35
DVDD
Clock Generator
(Primary Clock System)
34
TEST
33
BFVSS
32
BFVDD
26
27
28
29
30
31
VIN
DRAIN
7
6
START–UP CIRCUIT
UVLO
COMPARATOR
–
–
START–UP
+
+
CIRCUIT
VCC (START)/
VCC (STARTUP OFF)/
VCC (STOP)
VCC (STARTUP ON)
Q1
SOFT DRIVE
CIRCUIT
S
Q
R
OCP THRESHOLD
COMPARATOR
VTH (OCL)
BURST MODE
OCP THRESHOLD
COMPARATOR
RESTART
TIMER
VTH (BURST LIMIT)
5
SOURCE/OCL
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