Schematic Diagram - Main Section (8/12) - Sony DVP-NS3100ES Service Manual

DVP-NS3100ES
7-17. SCHEMATIC DIAGRAM – MAIN SECTION (8/12) –
256FS_DAC
CLK_5V
CLK_GND
(Page 44)
DAC_SCLK
DAC_LRCK
C1
(Page 39)
C2
C3
C4
C5
(Page 39)
DSD8_DAC
DSD8_DAC
DSD11_DAC
DSD11_DAC
DSD9_DAC
DSD9_DAC
DSD0_DAC
DSD0_DAC
DSD1_DAC
DSD1_DAC
DSD4_DAC
DSD4_DAC
DSD5_DAC
(Page 38)
DSD5_DAC
DSD2_DAC
DSD2_DAC
DSD3_DAC
DSD3_DAC
DLDRO_CS
DLDRO_CS
FLFRO_CS
FLFRO_CS
SLSRO_CS
SLSRO_CS
(Page 36) CSWO_CS
CSWO_CS
SCLK
SCLK
SO
(Page 36)
SCLK
SCLK
SO
(Page 39)
P_MUTE
P_MUTE
IF_RESET
IF_RESET
IF_ADAC_RST
AMUTE
SPDIF_SW
(Page 37)
BE_A_MUTE
(Page 35)
3.3V-EVER
(Page 36)
L1
L2
(Page 39)
DVP-NS3100ES
• See page 57 for IC Block Diagrams.
(8/12)
IC554
SN74LV541APWR
BUFFER
SO
SO
R561
0
R574
47k R575
47k
R576
47k
Q575
DTC144EKA-T146
R564 C594
100 0.01
Q574 R565
DTC144EKA-T146 100
C599 C595
0.1 0.01
Q574,575
MUTING SWITCH
C562
0.1
R556
100
C593
0.01
SWITCHING
R568 47
R567 47
DSD8_DAC
DSD11_DAC
DSD9_DAC
RB561
47
C563
0.1
DSD0_DAC
C590
10
DSD1_DAC
DSD4_DAC
DSD5_DAC
DSD2_DAC
DSD3_DAC
R563 0
P_MUTE
SWITCHING IF_RESET R569 0
IC558
R566 0
TC7SH08FU-TE85R
SCLK
VCC
SO
GND
DLDRO_CS
FLFRO_CS
SLSRO_CS
CSWO_CS
FB593 FB552
VCC
R560 FB551
47 0
GND
IC553
TC7SH08FU-TE85R
40 40
CLK_GND
256FS_DAC
CLK_5V
CLK_GND
CLK_SW
256FS_OSC
CLK_GND
PCM_SCLK
DGND
PCM_LRCK
DGND
DSD_CLK
DGND
DL
(Page 47)
DGND
DR
DGND
ADY_DLDRO
DGND
FL
DGND
FR
DGND
ADY_FLFRO
DGND
CN552
25P
CN551
29P
DGND
SL
DGND
SR
DGND
ADY_SLSRO
DGND
C
DGND
SW
DGND
ADY_CSWO
DGND
ADAC_RST
P_MUTE
P-DET
(Page 47)
AMUTE
SCLK
DGND
SO
DGND
DLDR_CS
FLFR_CS
SLSR_CS
CSW_CS
D3V
DGND
SPDIF
DGND