Schematic Diagram - Main Section (3/12) - Sony DVP-NS3100ES Service Manual

Hide thumbs Also See for DVP-NS3100ES:
Table of Contents

Advertisement

7-12. SCHEMATIC DIAGRAM – MAIN SECTION (3/12) –
(3/12)
+1.8V REGULATOR
IC318
µPC2918T-E1
DD3.3V_BE
I
G O
DD3.3V_1
C250
0.1
(Page 36)
DGND
27M_BE
(Page 44)
+1.8V REGULATOR
IC308
TK11118CSCL-G
C252
0.1
C308
C256
47
0.01
6.3V
C254
0.1
BE_SCL
BE_SCL
BE_SDA
BE_SDA
FE_RST
FE_RST
FE_IRQ
FE_IRQ
B_ERROR
B_ERROR
B_WCLK
B_WCLK
XBCLK
XBCLK
XPCLK
XPCLK
(Page 33)
XDATA
XDATA
B_SYNC
B_SYNC
B_V4
B_V4
I2S_BFLAG_OUT
I2S_BFLAG_OUT
I2S_SYNC_OUT
I2S_SYNC_OUT
I2S_WCK_OUT
I2S_WCK_OUT
I2S_DATA_OUT
I2S_DATA_OUT
I2S_BCLK_OUT
I2S_BCLK_OUT
(Page 38)
DVP-NS3100ES
• See page 53 for Waveforms. • See page 59 for IC Block Diagrams. • See page 66 for IC Pin Function Description.
C357
10
FL318
C285
0.01
FL303
C326
0.1
C318
C303
C258
C272
C346
180
C324
180
0.1
0.1
0.001
6.3V
0.001
6.3V
R285
10k
R260
47
C270
0.1
C341
0.01
R282
10k
R269
0
R268
0
R270
10k
R266
0
R264
0
R267
10k
R265
10k
R278
0
R277
10k
R274
R275
47
10k
F_OE
C327
10
C339
0.01
C269
0.1
C267
C350
C340
0.1
0.01
10
R254
100
C264
0.01
SA_IRQ
C263
100p
R259
10k
C262
100p
R256
0
R258
10k
C261
100p
R257
10k
R273
10k
F_WE
R272
47
R281
10k
SA_RW
R276
0
SA_WAIT
F_CE
R271
100
SA_CS
R263
0
FJ_CE
R262
100
C342
C271
0.01
0.1
DATA0
RB252
47
DATA1
DATA2
DATA3
DATA4
RB251
47
DATA5
DATA6
DATA7
C328
10
C268
0.1
C274
0.01
DATA8
R280
47
DATA9
R279
47
DATA10
DATA11
DATA12
DATA13
RB250
47
C277
0.1
R317
4.7k
C300
10
C296
0.1
CPU
IC256
STE5588CVB
R338
10k
C309
22p
R299
10k
C306
C334
22p
10
C301
R353
R328
0.1
10k
1.8k
C321
22p
C330
0.01
(Page 36)
35
35
512FS_BE
SPDIF
SPDIF
PCM_LRCK
PCM_LRCK
512FS_BE
PCM_SCLK
PCM_DATA2
PCM_DATA3
PCM_DATA1
PCM_DATA2
PCM_DATA0
PCM_DATA1
PCM_DATA0
SI
RB263
47
BE_A_MUTE
YC_CLKOUT
YC0
YC1
YC2
YC3
YC4
R315
47
PCM_SCLK
YC5
YC6
C347
C319
C315
0.1
0.01
10
YC7
L318
1µH
VIDEO_RST
C317
0.01
RB265
47
YC7
YC6
YC5
LETTER
YC4
SQUEEZE
RB264
47
YC3
YC2
YC1
YC0
C316
C336
R343
0.01
10
10k
RB272
C332
0
0.1
H_INT_B
H_SDA_BP
H_SCL_BP
BE_SDA
R344
BE_SCL
10k
R358
47
XRCLR
R357
0
B_V4
R356
0
B_WCLK
B_SYNC
R354
2.7k
XPCLK
XBCLK
XDATA
C335
10
C343
0.1
C331
0.01
RB271
47
R350
10k
VIDEO_RST
R351
0
R348
47
I2S_BFLAG_OUT
R347
47
I2S_BCLK_OUT
R346
47
I2S_DATA_OUT
C322
0.01
C358
0.1
R345
47
YC_CLKOUT
R363
47
FB262
0
PCM_DATA3
ADDR1
FUR_RST
ADDR2
ADDR3
ADDR4
R349
10k
ADDR5
ADDR6
ADDR7
DATA0
DATA1
C276
10
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
R330
10
DATA11
DATA12
DATA13
DATA14
R296
0
DATA15
SA_CS
SA_IRQ
SA_WAIT
SA_RW
FUR_RST
DVP-NS3100ES
B1
(Page 36)
B2
(Page 36)
512FS_BE
(Page 44)
SPDIF
PCM_LRCK
PCM_SCLK
PCM_DATA3
PCM_DATA2
PCM_DATA1
(Page 39)
PCM_DATA0
SI
BE_A_MUTE
(Page 40)
YC_CLKOUT
YC0
YC1
YC2
YC3
YC4
YC5
(Page 41)
YC6
YC7
VIDEO_RST
LETTER
SQUEEZE
(Page 43)
R367
0
HDMI_+5VCONT_IF
(Page 37)
HDMI_+5VCONT
H_INT_B
(Page 42)
BE_SDA
BE_SCL
(Page 41)
TMODE_SW
BE_CS
BE_BUSY
BE_TXD
BE_RXD
(Page 37)
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
(Page 38)
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
SA_CS
SA_IRQ
SA_WAIT
SA_RW
FUR_RST

Advertisement

Table of Contents
loading

Table of Contents