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3
Pin Number
3, 5, 7, 9, 11, 13,
15, 17
2, 4, 6, 8, 10, 12,
14, 16, 18, 20, 22,
24, 26, 28, 30
19
21
37
38
23
1, 25, 27, 29, 31,
32, 33, 34, 35, 36,
40
39
MOTOROLA
3-6
Table 3-1.
Logic Analyzer Connector P1 Signal Descriptions
Signal Mnemonic
AD7-AD0
LA14-LA0
/LIR
R/W
/IRQ
/RESET
PHI2
GND
Vdd
Signal Name and Description
Data bus:- MCU bidirectional data bus.
Address bus:- MCU output address bus.
Load Instruction Register:- Active-low output
signal, asserted when an instruction starts.
Read/Write:- Output signal that indicates the
direction of data transfer.
MCU Interrupt Request:- Active-low input sig-
nal from the target that asynchronously applied
an MCU interrupt.
Reset:- Active-low bidirectional signal for start-
ing an EVS reset.
PHI2 clock:- Internally generated output clock
signal used as a timing reference.
Ground
+5Vdc power:- Input voltage (+5Vdc @
1A(max)) used by the EVS logic circuits.
HC05BS8EM USER'S MANUAL
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