Modes Of Operation; Clocking Scheme - Nokia 301 Service Manual

RM-839; RM-840; RM-841
System Module

Modes of operation

When the system enters sleep mode, most devices can be put into off or standby mode such as the LDOs and
DC/DC converter, to minimize quiescent current. The DC/DC converter can be programmable into its low power
mode (PFM) and VCORE changes the output voltage to a lower value. The HPBG (HIGH PRECISION BANDGAB) is
deactivated and the DCXO in RF is switched off. Exit from sleep mode is initiated by expiration of the sleep
timer or detection of a HW interrupt.

Clocking scheme

The X-GOLD™ 614 integrates in its Clock Generation Unit (CGU) a powerful clocking scheme which includes
clock flexibility during normal operation combined with possibilities to minimize power dissipation by
special clock settings for standby and low power modes.
The CGU architecture simplifies the clock frequency control required for voltage scaling.
Figure 43 Clock concept overview
Two separate clock inputs are provided, a 26 MHz high swing input and a 32.768 kHz square wave input. The
32.768 kHz clock can also be generated by an on-chip oscillator. The 26 MHz input clock, or the 32.768 kHz
clock, may be used in power saving modes to clock the X-GOLD™ 614.
During normal operation PLLs with single output frequencies and PLLs with additional phaseshifter outputs
generate different clocks derived from the shaped 26 MHz input clock.
The clocks for high speed serial interfaces are generated with an additional PLL located near the interface
pads. The PLL and phaseshifter clocks as well as the input clock, and the 32.768 kHz clock are selected by
glitch free synchronous multiplexers for the different clock subsystems. The multiplexers allow flexible choice
of either of these clocks as master clock, independent for each master clock.
From the master clocks the additional clocks for different peripherals and buses are derived by dividers in
the CGU. The outputs of these dividers or the master clocks themselves are distributed to the clock subsystems.
The main clock subsystems are:
• The main clock subsystems are :
• The crossbar clocks and the AHB peripheral bus systems.
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