Panasonic CQ-C8351N Service Manual page 16

CQ-C8351N / CQ-C8301N / CQ-C7301N
Pin Port
No.
56 DVDD3 I/O system (3.3V) power supply
57 DVSS3 GND
58 REST SW Mechanics deck REST SW input
59 DATA M C AUDIO serial data output
60 SO Serial data output
61 /IACK(NC) No Connection
62 HBL(NC) No Connection
63 /NMI
64 /INT0
65 /INT1
66 BLKCK Subcode block clock pulse input
67 /INT3
68 CV DD4 CORE CPU system (1.6V) power
supply
69 SW1 Mechanics deck SW1 input
70 CVSS7 GND
71 MCLK Clock output (To Servo DSP)
72 DVSS4 GND
73 MLD Command load signal output (To
Servo DSP)
74 MDATA Command data output (To Servo
DSP)
75 DVDD4 I/O system (3.3V) power supply
76 DVSS5 GND
77 CLK MD1 Clock mode setting (L fixation)
78 CLK MD2 Clock mode setting (H fixation)
79 CLK MD3 Clock mode setting (L fixation)
80 HPI60 No Connection
(NC)
81 SW2 Mechanics deck SW2 input
82 TOUT(NC) No Connection
83 EMU0
84 EMU/OFF
85 TDO
86 TDI
87 /TRST
88 TCK
89 TMS
90 CVSS8 GND
91 CVDD5 CORE CPU system (1.6V) power
supply
92 HPIENA GND
93 DVSS6 GND
94 CLKOUT No Connection
95 CLKENA Oscillation output Cainabl signal
96 X1 Crystal Connection
97 X2/CLKIN Crystal Connection
98 RS Reset signal input
99 D0 Data base of FLASH ROM
100 D1
101 D2
102 D3
103 D4
104 D5
105 A16 Address bus of FLASH ROM
106 DVSS7 GND
107 A17 Address bus of FLASH ROM
108 A18 Address bus of FLASH ROM
109 A19 TP419
110 A20 TP416
111 CVSS9 GND
112 DVDD5 I/O system (3.3V) power supply
113 D6 Data bus of FLASH ROM
114 D7
115 D8
116 D9
117 D10
Descriptions I/O
-
-
I
O
O
-
-
- -
- -
- -
I
- -
-
I
-
O
-
I
O
-
-
I
I
I
-
I
-
- -
- -
- -
- -
- -
- -
- -
-
-
I
-
-
O
O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
O
-
O
O
O
O
-
-
I/O
I/O
I/O
I/O
I/O
(V) Pin Port
No.
3.1 118 D11 Data bus of FLASH ROM
0 119 D12
3.1 120 STAT Status signal input
1.6 121 D13 Data path of FLASH ROM
1.1 122 D14
- 123 D15
- 124 HD5(NC) No Connection
3.1 125 CVDD6 CORE CPU system (1.6V) power
supply
3.1
126 CVSS10 GND
3.1
127 /HDS1(NC) No Connection
0
128 DVSS8 I/O system (3.3V) power supply
3.1
129 /HDS2(NC) No Connection
1.6
130 DVDD6 I/O system (3.3V) power supply
0 131 A0 Address bus of FLASH ROM
0 132 A1
3.1 133 A2
0 134 A3
3.1 135 /RST Reset signal output(To Servo
DSP)
3.1 136 A4 Address bus of FLASH ROM
137 A5
3.1
138 A6
0
139 A7
0
140 A8
3.1
141 A9
0
142 CVDD7 CORE CPU system (1.6V) power
- supply
143 A12 TP406
0.2
144 DVSS9 GND
-
3.1
3.1
0
3.1
0
3.1
3.1
0
1.6
0
0
-
0
0.7
1.0
3.1
0
0
0
0
0
0
3.1
0
3.1
0
0
0
0
3.1
0
0
0
0
0
16
Descriptions I/O
I/O
I/O
I
I/O
I/O
I/O
-
-
-
-
-
-
-
O
O
O
O
O
O
O
O
O
O
O
-
-
-
(V)
0
0
3.0
3.1
0
0
-
1.6
0
-
0
-
3.1
3.1
0
0
0
3.1
0
3.1
3.1
0
3.1
3.1
1.6
0
0