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Supports a maximum clock of 6.8MHz.
Signals: TX (SPI_DO, MISO), RX (SPI_DI, MOSI), CTS_N (SPI_CLK) and RTS_N (SPI_SS_N)
At system level the slave has no way of forcing data to the master to indicate it is ready for transmission;
the master must poll the client periodically. Since the specified idle byte pattern for both receive and
transmit is A7 B4, the master can transmit this idle pattern into the slave repeatedly.If the master
receives idle patterns back from the slave, it indicates that the slave currently has nothing to transmit
but is ready to communicate. Default protocol is NMEA (protocol can be configured by NMEA
$PSRF100 message).
On the receive side, the host is expected to transmit idle pattern A7 B4 when it is querying the
module's transmit buffer, unless it has traffic to send to the module. In this way, the volume of
discarded bytes is kept nearly as low as in the UART implementation because the hardware does
not place most idle pattern bytes in its RX FIFO.
The FIFO thresholds are placed to detect large messages requiring interrupt-driven servicing. On the
transmit side, the intent is to fill the FIFO only when it is disabled and empty. In this condition, the SPI
driver software loads as many queued messages as can completely fit in the FIFO. Then the FIFO is
enabled. The host is required to poll messages until idle pattern bytes are detected. At this point the
FIFO is empty and disabled, allowing the SPI driver to again respond to an empty FIFO interrupt and
load the FIFO with any messages in queue.
Figure 2: SPI host port timing diagram, SPI mode 1 (assuming one byte transfer)
2.2.3
Dead Reckoning I2C bus
The DR_I2C bus (master) provides optional connectivity to the following devices:
GTS-4E GPS Module Hardware Integration Manual
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