Holtek HT46R65 Manual

A/d with lcd type 8-bit mcu

Hide thumbs Also See for HT46R65:

Handbook (194 pages)

page of 48

/ 48
Bookmarks

Quick Links

Download this manual

Technical Document

Tools Information

FAQs

Application Note

HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM

HA0004E HT48 & HT46 MCU UART Software Implementation Method

HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series

HA0047E An PWM application example using the HT46 series of MCUs

Features

Operating voltage:

=4MHz: 2.2V~5.5V

SYS

=8MHz: 3.3V~5.5V

SYS

24 bidirectional I/O lines

Two external interrupt input

Two 16-bit programmable timer/event counter with

PFD (programmable frequency divider) function

LCD driver with 41´3 or 40´4 segments

(logical output option for SEG0~SEG23)

8K´16 program memory

384´8 data memory RAM

Supports PFD for sound generation

Real Time Clock (RTC)

8-bit prescaler for RTC

Watchdog Timer

General Description

The HT46R65/HT46C65 are 8-bit, high performance,

RISC architecture microcontroller devices specifically

designed for A/D product applications that interface di-

rectly to analog signals and which require LCD Inter-

face. The mask version HT46C65 is fully pin and

functionally compatible with the OTP version HT46R65

device.

The advantages of low power consumption, I/O flexibil-

ity, timer functions, oscillator options, multi-channel A/D

Rev. 1.90

HT46R65/HT46C65

A/D with LCD Type 8-Bit MCU

Buzzer output

On-chip crystal, RC and 32768Hz crystal oscillator

HALT function and wake-up feature reduce power

consumption

16-level subroutine nesting

8 channels 10-bit resolution A/D converter

4-channel 8-bit PWM output shared with 4 I/O lines

Bit manipulation instruction

16-bit table read instruction

Up to 0.5ms instruction cycle with 8MHz system clock

63 powerful instructions

All instructions in 1 or 2 machine cycles

Low voltage reset/detector function

52-pin QFP, 56-pin SSOP, 100-pin QFP packages

Converter, Pulse Width Modulation function, HALT and

wake-up functions, in addition to a flexible and

configurable LCD interface enhance the versatility of

these devices to control a wide range of applications re-

quiring analog signal processing and LCD interfacing,

such as electronic metering, environmental monitoring,

handheld measurement tools, motor driving, etc., for

both industrial and home appliance application areas.

February 14, 2006

Table of Contents

Need help?

Do you have a question about the HT46R65 and is the answer not in the manual?

Questions and answers

Summary of Contents for Holtek HT46R65

Page 1 The mask version HT46C65 is fully pin and quiring analog signal processing and LCD interfacing, functionally compatible with the OTP version HT46R65 such as electronic metering, environmental monitoring, device.
Page 2: Block Diagram
HT46R65/HT46C65 Block Diagram Rev. 1.90 February 14, 2006...
Page 3: Pin Assignment
HT46R65/HT46C65 Pin Assignment H T 4 6 R 6 5 / H T 4 6 C 6 5 1 0 0 Q F P - A H T 4 6 R 6 5 / H T 4 6 C 6 5...
Page 4 HT46R65/HT46C65 Pin Description Pin Name Options Description PA0/BZ Bidirectional 8-bit input/output port. Each bit can be configured as wake-up in- Wake-up PA1/BZ put by ROM code option. Software instructions determine the CMOS output Pull-high or Schmitt trigger input with or without pull-high resistor (determined by...
Page 5 HT46R65/HT46C65 D.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ ¾ =4MHz Operating Voltage ¾ ¾ =8MHz ¾ No load, ADC Off, Operating Current =4MHz (Crystal OSC, RC OSC) ¾ Operating Current No load, ADC Off, ¾...
Page 6 HT46R65/HT46C65 Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ LCD Common and Segment =0.1V Current ¾ -160 ¾ LCD Common and Segment =0.9V Current -180 -360 ¾ ¾ Pull-high Resistance of I/O Ports and INT0, INT1 ¾ ¾...
Page 7: Functional Description
HT46R65/HT46C65 Functional Description Execution Flow After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by 1. The system clock is derived from either a crystal or an The PC then points to the memory word containing the RC oscillator or a 32768Hz crystal oscillator.
Page 8: Program Memory
HT46R65/HT46C65 · Location 008H The lower byte of the PC (PCL) is a readable and Location 008H is reserved for the external interrupt writeable register (06H). Moving data into the PCL per- service program also. If the INT1 input pin is activated, forms a short jump.
Page 9 HT46R65/HT46C65 Stack Register - STACK 0 0 H I n d i r e c t A d d r e s s i n g R e g i s t e r 0 0 1 H M P 0...
Page 10: Accumulator - Acc
HT46R65/HT46C65 Arithmetic and Logic Unit - ALU reset by ²SET [m].i² and ²CLR [m].i². They are also indi- rectly accessible through memory pointer registers This circuit performs 8-bit arithmetic and logic opera- (MP0;01H/MP1;03H). The space before 40H is overlap- tions and provides the following functions: ping in each bank.
Page 11 HT46R65/HT46C65 Interrupts sired control sequence, the contents should be saved in advance. The device provides two external interrupts, two internal timer/event counter interrupts, an internal time base in- External interrupts are triggered by a an edge transition terrupt, and an internal real time clock interrupt. The in- of INT0 or INT1 (ROM code option: high to low, low to terrupt control register 0 (INTC0;0BH) and interrupt...
Page 12 HT46R65/HT46C65 The real time clock interrupt is initialized by setting the register 1 (INTC1) which is located at 1EH in the RAM. real time clock interrupt request flag (RTF; bit 6 of EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all INTC1), that is caused by a regular real time clock sig- used to control the enable/disable status of interrupts.
Page 13 Watchdog Timer - WDT Multi-function Timer The WDT clock source is implemented by a dedicated The HT46R65/HT46C65 provides a multi-function timer RC oscillator (WDT oscillator) or an instruction clock for the WDT, time base and RTC but with different (system clock/4) or a real time clock oscillator (RTC os- time-out periods.
Page 14 HT46R65/HT46C65 Time Base Real Time Clock - RTC The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A, or The real time clock (RTC) is operated in the same man- a WDT overflow.
Page 15 HT46R65/HT46C65 Reset There are three ways in which reset may occur. · RES is reset during normal operation · RES is reset during HALT · WDT time-out is reset during normal operation The WDT time-out during HALT differs from other chip reset conditions, for it can perform a ²warm reset²...
Page 16 HT46R65/HT46C65 The register states are summarized below: Reset WDT Time-out RES Reset RES Reset WDT Time-out Register (Power On) (Normal Operation) (Normal Operation) (HALT) (HALT)* xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx xxxx uuuu uuuu uuuu uuuu...
Page 17 HT46R65/HT46C65 Timer/Event Counter register is changed by each writing TMR0H (TMR1H) operations. Reading TMR0H (TMR1H) will latch the Two timer/event counters (TMR0,TMR1) are imple- contents of TMR0H (TMR1H) and TMR0L (TMR1L) mented in the microcontroller. The Timer/Event Counter counters to the destination and the lower-order byte 0 contains a 16-bit programmable count-up counter and buffer, respectively.
Page 18 HT46R65/HT46C65 flow occurs, the counter is reloaded from the timer/event transient occurs again. In other words, only 1-cycle counter preload register, and generates an interrupt re- measurement can be made until the T0ON/T1ON is set. quest flag (T0F; bit 6 of INTC0, T1F; bit 4 of INTC1). In...
Page 19 HT46R65/HT46C65 To enable the counting operation, the Timer ON bit or 18H). For output operation, all the data is latched and (T0ON: bit 4 of TMR0C; T1ON: 4 bit of TMR1C) should remains unchanged until the output latch is rewritten.
Page 20 HT46R65/HT46C65 Input/Output Ports The PA0 and PA1 are pin-shared with BZ and BZ signal, PD0~PD3 data register will enable the PWM output function and writing ²0² will force the PD0~PD3 to re- respectively. If the BZ/BZ option is selected, the output signal in output mode of PA0/PA1 will be the buzzer sig- main at ²0².
Page 21 HT46R65/HT46C65 register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is The microcontroller provides 4 channels (6+2)/(7+1) the value of PWM.1~PWM.0. (dependent on options) bits PWM output shared with PD0/PD1/PD2/PD3. The PWM channels have their data...
Page 22 HT46R65/HT46C65 In a (7+1) bits mode PWM cycle, the duty cycle of each to set PB configurations. PB can be an analog input or modulation cycle is shown in the table. as digital I/O line decided by these 3 bits. Once a PB line...
Page 23 HT46R65/HT46C65 Bit No. Label Function ACS0 ACS1 Defines the analog channel select. ACS2 PCR0 Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is PCR1 power off to reduce power consumption PCR2 Indicates end of A/D conversion.
Page 24 HT46R65/HT46C65 The following programming example illustrates how to setup and implement an A/D conversion. The method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete. Example: using EOCB Polling Method to detect end of conversion...
Page 25 HT46R65/HT46C65 LCD Display Memory The device provides an area of embedded data memory for LCD display. This area is located from 40H to 68H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the RAM) is the switch between the RAM and the LCD display memory.
Page 26 HT46R65/HT46C65 D u r i n g a R e s e t P u l s e N o r m a l O p e r a t i o n M o d e H A L T M o d e...
Page 27 HT46R65/HT46C65 Low Voltage Reset/Detector Functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5;...
Page 28 HT46R65/HT46C65 Options The following shows the options in the device. All these options should be defined in order to ensure proper functioning system. Options OSC type selection. This option is to decide if an RC or crystal or 32768Hz crystal oscillator is chosen as system clock.
Page 29: Application Circuits
HT46R65/HT46C65 Application Circuits R C S y s t e m O s c i l l a t o r S e e r i g h t s i d e C r y s t a l S y s t e m...
Page 30: Instruction Set Summary
HT46R65/HT46C65 Instruction Set Summary Instruction Flag Mnemonic Description Cycle Affected Arithmetic ADD A,[m] Add data memory to ACC Z,C,AC,OV ADDM A,[m] Add ACC to data memory Z,C,AC,OV ADD A,x Add immediate data to ACC Z,C,AC,OV ADC A,[m] Add data memory to ACC with carry...
Page 31 HT46R65/HT46C65 Instruction Flag Mnemonic Description Cycle Affected Branch JMP addr Jump unconditionally None SZ [m] Skip if data memory is zero None SZA [m] Skip if data memory is zero with data movement to ACC None SZ [m].i Skip if bit i of data memory is zero None SNZ [m].i...
Page 32: Instruction Definition
HT46R65/HT46C65 Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added si- multaneously, leaving the result in the accumulator. ACC ¬ ACC+[m]+C Operation Affected flag(s) ¾...
Page 33 HT46R65/HT46C65 AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND op- eration. The result is stored in the accumulator. ACC ¬ ACC ²AND² [m] Operation Affected flag(s) ¾...
Page 34 HT46R65/HT46C65 CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. [m].i ¬ 0 Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared.
Page 35 HT46R65/HT46C65 CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged.
Page 36 HT46R65/HT46C65 HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Page 37 HT46R65/HT46C65 MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. ACC ¬ x Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory...
Page 38 HT46R65/HT46C65 Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter ¬ Stack Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator...
Page 39 HT46R65/HT46C65 RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re- places the carry bit; the original carry flag is rotated into the bit 0 position.
Page 40 HT46R65/HT46C65 RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator.
Page 41 HT46R65/HT46C65 SET [m] Set data memory Description Each bit of the specified data memory is set to 1. [m] ¬ FFH Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1.
Page 42 HT46R65/HT46C65 SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ¬ ACC+[m]+1 Operation Affected flag(s) ¾ ¾ Ö Ö Ö Ö...
Page 43 HT46R65/HT46C65 SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles).
Page 44 HT46R65/HT46C65 XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclu- sive_OR operation and the result is stored in the accumulator. ACC ¬ ACC ²XOR² [m] Operation Affected flag(s) ¾...
Page 45: Package Information
HT46R65/HT46C65 Package Information 52-pin QFP (14´14) Outline Dimensions Dimensions in mm Symbol Min. Nom. Max. ¾ 17.3 17.5 ¾ 13.9 14.1 ¾ 17.3 17.5 ¾ 13.9 14.1 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 0.73 1.03 ¾...
Page 46 HT46R65/HT46C65 56-pin SSOP (300mil) Outline Dimensions Dimensions in mil Symbol Min. Nom. Max. ¾ ¾ ¾ ¾ C¢ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 0° 8° Rev. 1.90 February 14, 2006...
Page 47 HT46R65/HT46C65 100-pin QFP (14´20) Outline Dimensions Dimensions in mm Symbol Min. Nom. Max. ¾ 18.50 19.20 ¾ 13.90 14.10 ¾ 24.50 25.20 ¾ 19.90 20.10 ¾ ¾ 0.65 ¾ ¾ 0.30 ¾ 2.50 3.10 ¾ ¾ 3.40 ¾ ¾ 0.10 ¾...
Page 48 Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as- sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used...

This manual is also suitable for:

Ht46c65