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Holtek BC45B4523 Manual

13.56mhz multi-standard nfc reader
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Features
• Operating Voltage:
Receiver A_V
: 2.7V~3.6V
♦
DD
Transmitter T_V
: 2.7V~5.5V
♦
DD
Digital I/O IO_V
: 2.7V~5.5V
♦
DD
• Operating Temperature: -40°C~85°C
• Power Saving Modes:
Hard Power Down: 0.5μA
♦
Soft Power Down: 4.7μA
♦
Standby: 1.0mA
♦
Support Card Detection mode:
♦
10.4μA @ wakeup period=500ms
• Up to 10Mbps SPI interface speed
• 64-byte send and receive FIFO-buffer
• 64-byte addressing user-configurable registers
• Interrupt pin IRQ
• Programmable timer
• Low jitter on-chip oscillator buffer
• Ultra Low Power On-Chip 3.3V Regulator
• Low Power Card Detection
• External RF Field Detection
• Supported Protocols:
ISO14443A/B, all bit rates
♦
– 106, 212, 424 and 848kbps
ISO15693, all modes
♦
– Downlink: 1 of 4 and 1 of 256
– Uplink: 6.6/13/26/53kbps with 1 sub-carrier
– Uplink: 6.6/13/26kbps with 2 sub-carrier
– Package: 24-pin QFN
Transmitter
• Modulation index adjustable by software
• Output current up to 250mA @ T_V
• Output impedance 3Ω @ T_V
• Arbitrary modulation by external signal
• Wide operating voltage for TX from 2.7V to 5.5V
• On-chip framing coder for supported standards
Receiver
• RX sensitivity down to 2mVp
• On-chip Framing decoder for supported standards
• Automatic Gain Control (AGC)
Rev. 1.20
13.56MHz Multi-Standard NFC Reader
Applications
• Secure access control/door locks
• Toys
• Handheld NFC readers
• Contactless payment system
Abbreviation
AGC: Automatic gain control
CRC: Cyclic redundancy check
DPLL: Digital Phase locked Loop
EGT: Extra guard time in ISO14443B
EOF: End of Frame
ETU: Elementary Time Unit
fc: Carrier frequency
FIFO: First In, First Out Memory
SOF: Start of Frame
UID: Unique Identifier
RF: Radio Frequency
General Description
The BC45B4523 is a single-chip reader ASIC for
13.56MHz NFC/contactless standard protocols,
which provides the best solution for near field
wireless communication applications such as access
control locks, label readers, payment machines.
The device supports and compatibles with all major
global secured baseband ISO standards including
ISO14443 Type A, Type B, Crypto_M cards and
Smart label ISO15693. The device provides a high-
speed SPI controller/host interface with an integrated
64-byte FIFO for smooth data transfer. Furthermore,
=5.0V
the embedded codec is capable of handling all bit-
DD
=5.0V
level coding/decoding, encrypting/decrypting as well
DD
as frame-level manipulation for transmission and
reception. The device is well suited for mobile devices
due to its low power consumption and low operating
voltage from 2.7V to 3.6V. The ultra-low power on-
chip 3.3V regulator is provided to stabilize the device
power, and simultaneously supply power of up to
150mA to the external companion microcontroller.
The BC45B4523 receiver circuit has integrated a full
AGC loop allowing a wide dynamic range of RF input
signal levels. The excellent sensitivity performance of
the device enables detection of the input signals with
1
BC45B4523
October 28, 2020

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Summary of Contents for Holtek BC45B4523

  • Page 1 • Supported Protocols: General Description ISO14443A/B, all bit rates ♦ – 106, 212, 424 and 848kbps The BC45B4523 is a single-chip reader ASIC for ISO15693, all modes 13.56MHz NFC/contactless standard protocols, ♦ – Downlink: 1 of 4 and 1 of 256...

  • Page 2: Block Diagram

    The support a wide range of power supply voltages from BC45B4523 is offered in a QFN package with excellent 2.7V to 5.5V. A high drive current up to 250mA is heat dissipation when self-mounted on PCB.

  • Page 3: Pin Assignment

    BC45B4523 Pin Assignment VREG_IN T_VSS BC45B4523 MISO 24 QFN-A T_VDD MOSI T_VSS 7 8 9 10 11 12 Pin Description Pin No. Pin Name Type Description Analog Input Receiver input Analog Output Analog Test pin MISO Digital Output SPI: Master In Slave Out...

  • Page 4: Electrical Characteristics

    BC45B4523 Electrical Characteristics Absolute Maximum Rating Stresses exceeding those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to the absolute maximum rating conditions for an extended period of time may affect the device reliability. Only one absolute maximum rating can be applied at a time.

  • Page 5: Pin Characteristics

    BC45B4523 Symbol Parameter Conditions Min. Typ. Max. Unit Active state (CODEC on) — Idle state (CODEC off) — Hard Power Down (pin RSTPD=1) — — μA Soft Power Down (bit PowerDown=1), — μA 25°C Digital I/O Power Supply Current Soft Power Down (bit PowerDown=1),...

  • Page 6: Transmitter Characteristics

    BC45B4523 Transmitter Characteristics Symbol Parameter Conditions Min. Typ. Max. Unit Transmitter Current, Continuous I_TX =5V, 25°C, Average Current — — Wave Minimum Equivalent TX Output Z_TX,min =5V, 25°C — Ω Impedance (TxCfgCW=0x3F) Pin TX1 & TX2 are unconnected Transmitter Static Power Supply...

  • Page 7: Regulator Characteristics

    BC45B4523 Regulator Characteristics Symbol Parameter Conditions Min. Typ. Max. Unit Regulator Input Voltage — REG_IN Regulator Output Voltage =10mA, 25°C 3.25 3.30 3.35 REG_OUT Output Regulator Current — — — ∆Vout Line Regulation (∆Vout) =0mA, 3.6V < V < 5.5V —...

  • Page 8: Peripheral Specifications

    RF connection of the BC45B4523, whereas the receiver senses the topologies. The envelope of the input signal is filtered tag-modulated signal from the envelope of RF carrier and amplified with optional control by an automatic through the voltage divider.
  • Page 9 BC45B4523 +5.0 V from USB Power +3.3 V Power 100nF 100nF 10µF 10µF 100nF RSTPD BC45B4523 VMID (3.3V) 100nF MOSI MISO XTAL1 XTAL2 27.12MHz Typical Operating Circuit for External Power Supply (Not Apply On-Chip 3.3V Regulator) +5.0 V from USB Power +3.3 V...

  • Page 10: Spi Interface

    SPI Interface The BC45B4523 can be interfaced through a standard 4-wire SPI interface in order to access to internal registers. The SPI interface is capable of handling input stream with a speed of up to 10Mbps. There are 4 modes available where their timing diagrams are depicted in the following figures.
  • Page 11 BC45B4523 “1” indicated read command Register address MOSI A[5] A[4] A[3] A[2] A[1] A[0] MISO D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Command Read Output data SPI Interface for Single Register/Single Byte Read 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32...

  • Page 12: Register Overview

    BC45B4523 Registers Register Overview The device consists of 6-bit addressable registers which is grouped into 2 sectors. Each sector separated into multiple pages by their functions. There are 4 types of registers, namely Dynamic, Write Only, Read/Write and Read Only, in which their behaviours are described in the following table. The overview of the registers is shown in the “Register List”...
  • Page 13 BC45B4523 Page Addr. Register Name Reserved Reserved RxWait RxWait[7:0] ChannelRedundancy — MSBFirst CRC3309 CRC8 RxCRCEn TxCRCEn ParityOdd ParityEn CRCPresetMSB CRCPresetMSB[7:0] CRCPresetLSB CRCPresetLSB[7:0] ADC_ ADCCtrl — — ADC_Delay[1:0] FD_MinLvl ADC_Rsln Reserved FastMode ADC_Result_I ADC_Result_I[7:0] ADC_Result_Q ADC_Result_Q[7:0] — — — — —...
  • Page 14 BC45B4523 Page Addr. Register Name TxFallingCtrl TxOvsT1Fall[3:0] TxOvsT2Fall[3:0] TxRisingCtrl TxOvsT1Rise[3:0] TxOvsT2Rise[3:0] TxCfgFall — — TxCfgFall[5:0] TxCfgRise — — TxCfgRise[5:0] — — — — — — — — — — — — — — — — — — — — —...

  • Page 15: Register Details

    BC45B4523 Register Details Sector 0 – Page 0: Command and Status • Sector Select Register This register is used for sector selection. Address Name — — — — — — — Sector 0x00 Type — — — — — —...
  • Page 16 BC45B4523 • PrimaryStatus Register This register contains flags for indicating the status of modem, interrupt and FIFO. Address Name — ModemState[2:0] HiAlert LoAlert 0x03 Type — Reset Value — Bit 7 Unimplemented, read as “0” ModemState[2:0]: Indicate the state of RX, TX and FIFO Bit 6~4 000: Idle –...
  • Page 17 BC45B4523 Bit 6 RF_Det: RF field detection indication RF_Det being set to 1 indicates that external RF field level is higher than threshold level after execute FieldDetect command or WkUpCD Power Saving Mode. Bit 5 CRCReady: CRC ready indication CRCReady being set to 1 indicates that the CRC co-processor is in idle state and ready to operate.

  • Page 18: Interruptrequest Register

    BC45B4523 • InterruptRequest Register This register contains the interrupt request bits. Address Name SetIRq CDIRq TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq 0x07 Type Reset Value Bit 7 SetIRq: Interrupt request setup SetIRq is a mask bit used in resetting interrupt request bits. Clearing this bit to 0 makes the interrupt request bits, which are written with 1, cleared.

  • Page 19: Control Register

    BC45B4523 Sector 0 – Page 1: Control and Status • Control Register This register contains the control bits for all operation of reader system. Address Name — WkUpCD StandBy PowerDown Crypto_MOn TStopNow TStartNow FlushFIFO 0x09 Type — Reset Value —...
  • Page 20 BC45B4523 Bit 3 CRCErr: CRC error CRCErr will be set to 1 if RxCRCEn is set and the comparison between received CRC and calculated CRC giving a mismatched result. CRCErr is automatically cleared to 0 every time the receiver starts to receive.
  • Page 21 BC45B4523 • CRCResultMSB Register This register contains the CRC result. Address Name CRCResultMSB[7:0] 0x0E Type Reset Value Bit 7~0 CRCResultMSB[7:0]: The most significant byte of the CRC result The value of this register is valid only if the CRCReady bit is set to 1.
  • Page 22 BC45B4523 Bit 3 Tx2Inv: If this bit is set to 1, TX2 will deliver an inverted 13.56MHz carrier. Tx2Cw: Bit 2 0: TX2 delivers a modulated 13.56MHz carrier 1: TX2 continuously delivers an un-modulated 13.56MHz carrier Bit 1 Tx2RFEn: 0: TX2 drives a constant following Tx2Inv 1: TX2 delivers a 13.56MHz carrier...
  • Page 23 BC45B4523 Bit 5~3 CoderRate[2:0]: Configure coder rate 000: 848kbps for ISO14443A 001: 424kbps for ISO14443A; 848kbps for ISO14443B 010: 212kbps for ISO14443A; 424kbps for ISO14443B 011: 106kbps for ISO14443A; 212kbps for ISO14443B 100: 106kbps for ISO14443B 101: ISO15693 11x: Reserved...
  • Page 24 BC45B4523 • TypeBTxFraming Register This register is used to difine framing for ISO14443B transmission. Address Name NoTxSOF NoTxEOF EOFWidth CharSpacing[2:0] SOFWidth[1:0] 0x17 Type Reset Value Bit 7 NoTxSOF: If this bit is set to 1, the SOF will be omitted from the transmitted framing.
  • Page 25 BC45B4523 Bit 1~0 Gain[1:0]: Define gain of the Amplifier manually when the AGC is turned off (AGCEn=0) 00: 12dB (4x) 01: 24dB (16x) 10: 36dB (64x) 11: 48dB (250x) • DecoderControl Register This register is used to control the decoder behaviours.
  • Page 26 BC45B4523 • RxThreshold Register This register is used to define a threshold of the bit decoder from the correlator. Address Name MinLevel[2:0] — CollLevel[2:0] — 0x1C Type — — Reset Value — — Bit 7~5 MinLevel[2:0]: This bit field is used to define the minimum signal strength at the decoder input that shall be accepted.
  • Page 27 BC45B4523 Bit 5 NoRxEOF: 0: A missing EOF generates a framing error 1: A missing EOF will be ignored and no framing error is reported HP2Off: Bit 4 If this bit is set to 1, the 2 highpass filter will be switched off.
  • Page 28 BC45B4523 • RxControl3 Register This register is used to control the receiver behaviours. Address Name BPSKDecMeth BPSKDataRec SOFSel15693 — — — EMD_Suppress SOF43A_5Bits 0x1F Type — — — Reset Value — — — Bit 7 BPSKDecMeth: Define the BPSK Decoding Method...
  • Page 29 BC45B4523 Sector 0 – Page 4: RF-Timing, Channel Redundancy and ADC Control • Reserved Register This register is reserved for internal settings. Address Name Reserved 0x20 Type Reset Value Bit 7~0 Reserved bits for internal settings. For proper operation, the register content must be fixed at “0000_1010”...
  • Page 30 BC45B4523 Bit 0 ParityEn: 0: No parity bit is inserted or expected (ISO14443B and ISO15693) 1: The parity is inserted in the transmitted data stream at the end of each byte and expected in the received data stream (ISO14443A) • CRCPresetMSB Register This register contains the most significant byte of the 16-bit preset value of the CRC Register.
  • Page 31 BC45B4523 Bit 1 ADC_Rsln: ADC resolution setup 0: 7 bits – 10.6mV 1: 8 bits – 5.3mV This bit is used to configure the ADC resolution which defines RF amplitude input at RX pin, Refer to the “RF Amplitude Detector System” section for more details. The defined resolution is based on RF input signal which is in phase with internal clock and ADC_FullscaleAdj (Sector1-0x05.[1:0])=“00”.
  • Page 32 BC45B4523 Bit 4~0 TPreScaler[4:0]: Define the timer clock (Ftimer) Ftimer=13.56MHz / (2 ), the value of TPreScaler bit field can be adjusted from 0 to 21. TPreScaler • TimerControl Register This register is used to setup the automatic start and stop of timer, which is triggered by events from RF.
  • Page 33 BC45B4523 Bit 6 WkTStopNow: Wake up timer immediate stop control Setting this bit to 1 stops the wake up timer (16.38kHz) immediately. Reading result from this bit is always “0”. This bit will be activated when the wake up timer is running.
  • Page 34 BC45B4523 Bit 6~4 FDDetectTime[2:0]: Define the number of detection time, FD_Times, in the Field Detection operation The equation of the FD_Times is: FD_Times=2 , refer to the “RF Amplitude Detector System” FDDetectTime section for more details. Bit 3~2 Unimplemented, read as “0”...
  • Page 35 BC45B4523 • FDThreshold_Q_H Register This register is used to setup the threshold level phase Q for field detection operation. Address Name FDThreshold_Q_H[7:0] 0x33 Type Reset Value Bit 7~0 FDThreshold_Q_H[7:0]: This bit field is used to define threshold level phase Q for external RF field, if ADC_Result_Q >...
  • Page 36 BC45B4523 • CDThreshold_Q_H Register This register is used to setup the high threshold level phase Q for card detect operation. Address Name CDThreshold_Q_H[7:0] 0x37 Type Reset Value Bit 7~0 CDThreshold_Q_H[7:0]: This bit field is used to define threshold level phase Q for card detect operation, when card is loaded to RF field driven by the device itself.
  • Page 37 BC45B4523 • Test Register This register is used for TD and TA pin configuration. Address Name Reserved Test[6:0] 0x3A Type Reset Value Bit 7 Reserved bit for internal setting, this bit must be fixed at “0” and can not be modified...
  • Page 38 BC45B4523 • Reserved Register This register is reserved for internal settings. Address Name Reserved 0x3D Type Reset Value Bit 7~0 Reserved bits for internal settings. For proper operation, the register content must be fixed at “1111_0000” and can not be modified •...
  • Page 39 BC45B4523 Bit 0 Sector: Define sector for register page control • LFOTrimResult Register This register indicates the low frequency oscillator trimming result. Address Name LFOTrimResult[7:0] 0x01 Type Reset Value “x”: Unknown Bit 7~0 LFOTrimResult[7:0]: Display the low frequency oscillator trimming result, which is trimmed after system start up or execute “LFOTune”...
  • Page 40 BC45B4523 Bit 1~0 CDIRqCfg[1:0]: Define the condition that IRq is set in CardDetect mode 00: ADC_Result_I or ADC_Result_Q is beyond the threshold level 01: ADC_Result_I is beyond the threshold level 10: ADC_Result_Q is beyond the threshold level 11: ADC_Result_I and ADC_Result_Q is beyond the threshold level •...
  • Page 41 BC45B4523 • ProductionParam Register This register shows the device production parameter. Address Name ProductionParam[7:0] 0x0E Type Reset Value “x”: Unknown ProductionParam[7:0]: Display the device production parameter, which is changed following Bit 7~0 production lot • Revision Register This register shows the device revision.
  • Page 42 BC45B4523 • TxCfgFall Register This register is used to configure TX1 and TX2 output conductance at falling edge of TX envelope. Refer to the “TX Overshoot Control” section for more details. Address Name — — TxCfgFall[5:0] 0x12 Type — —...
  • Page 43 BC45B4523 Bit 1~0 M_LP2[1:0]: Define low-pass cut-off frequency for the 2nd stage low pass filter 00: 2400kHz 01: 1200kHz 10: 683kHz 11: 363kHz • FilterAdjust Register This register is used for filter corner adjustment. Address Name ManFilterSel EnAutoTune — —...
  • Page 44 BC45B4523 Recommended Register Value for Normal Operation 15693 RX Protocol 15693 TX 15693 RX Man Default /Reset Addr. Data Rate 1/256 6.7k 6.7k Page Register Name Sector0 CRCResultLSB 0x63 0x63 0x63 0x63 0x63 0x9C 0x9C 0x9C 0x9C 0x9C 0x9C 0x9C 0x9C 0x9C...

  • Page 45: Crystal Oscillator

    Architecture and Peripherals Crystal Oscillator The BC45B4523 incorporates a stable low-jitter internal oscillator for generating a master clock for internal and external systems. The device accepts self crystal oscillator and external clock feeding. In certain applications, such as long range readers where noise is a major limiting factor, using an internal oscillator is recommended to obtain minimum jitter.
  • Page 46 BC45B4523 The driving behaviour of the transmitter is defined by the register TxControl (Sector0-0x11). By configuring the Tx1Inv, Tx2Inv, Tx2Cw, Tx2RFEn and Tx1RFEn bits, the driver can provide a differential modulated output, a single-ended modulated output or a plain carrier with a baseband signal for driving external circuitry. Setting the 100ASK bit makes the transmitter stops driving carrier during the modulation period.
  • Page 47 BC45B4523 Configuration Output Input Mode (ENV_Int) Tx2RFEn 100ASK TX2Cw Tx2Inv TX2 Conductance Logic Short to T_V TxCfgCW Modulation 100% ASK TxCfgCW RF_N TxCfgCW TxCfgCW CW on TX2, carrier derived (connect to external circuit) RF_N TxCfgCW TX2 Driver Behaviours on TxControl Combinations In case of an ASK modulation where the 100ASK is reset, the conductance of the drivers is controlled by two 6-bit bit fields, namely the TxCfgCW (Sector0-0x12.[5:0]) and TxCfgMod (Sector0-0x13.[5:0]), to create two different...
  • Page 48 BC45B4523 RF Signal Reg 0x11 0x4B TxCfgCW TxCfgCW TxCfgCW TxCfgCW 0x43 TxCfgCW TxCfgCW TxCfgCW TxCfgCW 0x5B TxCfgCW TxCfgCW TxCfgCW TxCfgCW 0x53 TxCfgCW TxCfgCW TxCfgCW TxCfgCW 0x46 Plain Carrier Output from class E amplifier RF Signal Pattern and Output Logic Level during Modulation The bit modulation pattern and the frame format for the operating standards can be configured using the register CoderControl (Sector0-0x14).
  • Page 49 BC45B4523 Besides, the output driver includes the non-overlapping clock to reduce the power due to leakage current from to ground during switching. TX_EN is an internal global control signal sent from the main control block operated in CardDetect and FieldDetect mode. When TX_EN is cleared, in FieldDetect operation, both the driver pins, the TX1 and TX2, are configured to Hi-Z state.
  • Page 50 BC45B4523 TxCfgCW TxCfgCW TxCfg- Rise TxCfgFall TX Example Waveform for Overshoot Control (100ASK=1, TxOvsT1Fall=0, TxOvsT2Fall=4, TxOvsT1Rise=0, TxOvsT2Rise=3) TxCfgCW TxCfgCW TxCfgRise TxCfg- Fall TxCfgMod TX Example Waveform for Overshoot Control (100ASK=0, TxOvsT1Fall=2, TxOvsT2Fall=3, TxOvsT1Rise=2, TxOvsT2Rise=4) Rev. 1.20 October 28, 2020...
  • Page 51 BC45B4523 RF Busy Indicator To monitor RF field transmission phase of the device, RF_Busy, the external control device or microcontroller need to reconstruct the device registers and signal behaviours as shown in the figure below. Write SPI Write SPI to WkUpCD mode...
  • Page 52 BC45B4523 Receiver The receiver part consists of an envelope detector, a voltage reference generator, an amplifier & filter system, a filter tuning system, a BPSK bit decoder, a Manchester-and-FSK bit decoder, a frame decoder and a timing control generator. The conceptual block diagram is shown as below.
  • Page 53 BC45B4523 SubCPulses[2:0] SubCCarrier[1:0] RxCoding[1:0] M_HP1[1:0] M_HP2[1:0] M_LP1[1:0] M_LP2[1:0] Encoder Gain_ST3 ManFilterSel ManFilterSel LP_Off HP2Off To Data Slicer Direct from RX Amp1 Amp2 Amp3 From Envelop Detector To Manchester & FSK Bit Decoder Filter Filter HighPass HighPass ByPassEnv LowPass LowPass TauAGC...
  • Page 54 BC45B4523 command is 302μs. However, the effect from temperature variation is not significant even if the whole IC is heated up by the driver. This process is performed every time the system is powered up. Therefore, it is not required to tune the filter frequently by users.
  • Page 55 BC45B4523 Analog BaseBand B2 > (CollLevel*A2) B3 > (CollLevel*A3) B1 < (CollLevel*A1) MinLevel Threshold Correlated Level Data Output Valid Collision Manchester-and-FSK Bit Decoder Output (ISO14443A) Standard / Coding MinLevel[2:0] CollLevel[2:0] ISO14443A / Manchester (No Anti-Collision) ISO14443A / Manchester (Anti-Collision) ISO15693 / Manchester...
  • Page 56 BC45B4523 ETU is an elementary time unit of the bit defined by t r[1:0] and the number of pulses in SubCpulses[2:0] as shown in the “ETU Interval” table below. The numbers in yellow boxes are practical numbers for existing modes in supported standards.
  • Page 57 BC45B4523 SubCpulses[2:0] Code Number of Pulse 32 Pulses 64 Pulses Scaling Factor (N) in Multiple of Clocks Standard Downlink Uplink RxWait BitPhase Miller – 106kbps Manch – 106kbps 0x07 0x3D Miller – 212kbps Manch – 106kbps 0x03* 0x88* ISO14443A Miller – 424kbps Manch –...
  • Page 58 BC45B4523 RF Amplitude Detector System TX_EN Transmitter ADC_EN VMID VREF ADC_Result_I ADC_Convert ADC_Result_Q RF_I ADC_Out_I CD_FD FieldDetect Control Mixer Pass RF_Q ADC_Out_Q Filter CardDetect ADC_Rsln ADC_FastMode ADC_FullScaleAdj ADC_Delay CLK_I CLK_Q FD_MinLvl CDTxDelay CDAverage FDAverage FDDetectTime Simplified RF Amplitude Detector System The device is capable to measure 13.56MHz sinewave amplitude at RX pin with a system shown in the above...
  • Page 59 BC45B4523 Effective RF Input Amplitude (mVp) Step Size ADC_FullScaleAdj [1:0] ADC_Rsln=0 (7 bits) ADC_Rsln=1 (8 bits) 10.6mVp 5.3mVp 8.0mVp 4.0mVp 13.1mVp 6.6mVp 15.9mVp 7.9mVp Effective RF Input Amplitude Step Size for ADC_FullScaleAdj and ADC_Rsln at RX Pin The following figure shows the basic operation in CardDetect mode. After CardDetect command is executed, the device will automatically disable transmitter by clearing TX_EN to 0.
  • Page 60 BC45B4523 FieldDetect Mode VMID External RF Field level TX_EN IdleIRq RxIRq ADC_EN ADC_Convert ADC_Result CDTxDelay Sense Process ADC_Delay Conversion Basic Timing for FieldDetect Mode The configuration of ADC_Delay and CDTxDelay are shown in the following tables respectively. ADC_Delay[1:0] ADC Delay Time 76μs...
  • Page 61 BC45B4523 FDDetectTime Operation detected ignored TX_EN IdleIRq RxIRq ADC_EN ADC_Convert ADC_Result ADC-1 ADC-2 ADC-3 ADC-4 Field Detection Operation when FDDetectTime=“010” FdDetectTime Repeating FDDetectTime Repeating [2:0] Times [2:0] Times FDDetectTime Configuration Normally, the system offset may induce error to conversion result. ADCCalibrate command should be prior executed to measure system offset and keep in internal buffer.

  • Page 62: Low Frequency Oscillator

    BC45B4523 Low Frequency Oscillator ManLFOTrim ManLFOTrimValue Low Frequency LFO_Code CLK 16.38kHz CLK 13.56MHz Oscillator LFOTrimResult ( LFO ) LFOTune Tuning Command Low Frequency Oscillator and Tuning Block Diagram The device contains tuneable low frequency oscillator, which generates clock 16.38kHz for wake up card detection system.
  • Page 63 BC45B4523 Writing to or reading from the FIFO can be performed through the register FIFOData (Sector0-0x02), while the amount of data remaining in the FIFO is shown by the register FIFOLength (Sector0-0x04). Handling data streams with lengths more than 64 bytes is possible by monitoring the status of flags LoAlert (Sector0-0x03.0) and HiAlert (Sector0-0x03.1), or using interrupt from LoAlertIRq (Sector0-0x07.0) or HiAlertIRq (Sector0-0x07.1).
  • Page 64 BC45B4523 Timer Unit General Timer The device contains a general timer unit where various events from the RF signal can trigger to start and stop. This feature aids the external microcontroller in monitoring RF events and enables interrupt-oriented programming. Especially in case of no response from air, interrupt from timer can indicate absence of the incoming signal within a given time.
  • Page 65 BC45B4523 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Timer Value Target Address (0x0C) is recognized MOSI Output data Addr : 0x0C : Timer MISO Timer (0x02) Point Timer Value is Latched The timer can be controlled by events listed below.
  • Page 66 BC45B4523 Default Register Address.Bit Indication Type Value Set to start the timer automatically after TX EOF is TStartTxEnd Sector0-0x2B.1 Read/Write transmitted Set to stop the timer automatically after TX SOF is TStartTxBegin Sector0-0x2B.0 Read/Write transmitted TReloadValue Sector0-0x2C Set the timer start values...

  • Page 67: Power Management

    BC45B4523 Register Address.Bit Indication Type Default Value Configure the wake up timer to restart WkTAutoRestart Sector0-0x2D.4 automatically after the counter reaches zero. Read/Write The timer restarts from WkTReloadValue WkTPreScaler Sector0-0x2D.[3:0] Clock Prescaler for wake up timer clock Read/Write 1001 WkTReloadValue Sector0-0x2E...
  • Page 68 BC45B4523 Card is appeared in the field TwkUp TwkUp WkT_Trig (Underflow) Detect Phase (Active) XTAL start up XTAL start up XTAL_Ready phase phase FD_Mode CDIRq CD_Mode TX_EN WkUpCD Mode Example Timing Diagram when WkFDEn=1 and WkCDGoActive=0 Card is appeared in the field...

  • Page 69: Interrupt System

    The device is comprised of seven sources of interrupts available to serve interrupt-oriented programming. The interrupts indicate key events related to the BC45B4523 peripherals, i.e., CODEC, FIFO, ADC and timer. When the interrupt requests occur, they are reported in three ways: a register InterruptFlag (Sector0-0x07), a bit IRQ (Sector0-0x03.3) in PrimaryStatus register and a signal level on pin IRQ.
  • Page 70 BC45B4523 register sets all interrupt enable bits. The InterruptFlag is usually set by the internal state machine and cleared by the external microcontroller, while InterruptEnable is always set and cleared by the external microcontroller. Suggested Action for Interrupt Flag Indication when Interrupt is Set...
  • Page 71 BC45B4523 Regulator The device contains an ultra low quiescent current on-chip 150mA regulators, which provides an output voltage of 3.3V. The typical connection is shown in the following figure. A 100nF ceramic capacitor and a 10μF tantalum capacitor are suggested to connect to the regulator output pin VREG_OUT for stability and supplying high frequency current to a particular section.

  • Page 72: Startup Command

    — — RF input amplitude at pin RX MaskSet + ReadSignature 0x31 Execute read out device signature ProductionParam + — Revision BC45B4523 Commands Startup Command Command Input Data Required Return Data Interrupt Action Code in FIFO...
  • Page 73 BC45B4523 The Transmit command conveys data from the FIFO buffer to the transmitter to modulate carriers. The RF bit pattern of the transmitted data is formed by following the defined protocol, configurable in transmitter-related register page (page 2). Basically, there are two basic schemes in transmitting data on air: Write-FIFO-before- Transmit and Transmit-before-Write-FIFO.

  • Page 74: Transmission Timing

    BC45B4523 Transmission Timing In case of transmitting data more than 64 bytes, the external microcontroller must input data to the FIFO during transmission before the last bit, where the FIFOLength is zero, is transmitted on-air. To transfer data without interruption, the FIFO level monitoring through low-alert interrupt must be employed. New data written after last- bit transmission is neglected and remains in the FIFO.
  • Page 75 BC45B4523 Register Address.Bit Indication/Usage Type Default Value CoderRate Sector0-0x14.[5:3] Configure transmitter data rate Read/Write TxCoding Sector0-0x14.[2:0] Configure transmitter coding Read/Write Define modulation width of data bit in ISO14443A ModWidth Sector0-0x15 Read/Write 0x0F and ISO15693 Define modulation width of SOF bit in ISO14443A...

  • Page 76: Collision Detection

    BC45B4523 Receive command to RX bit grid End of Transmission Command register Twait Wait until bit grid found TX_Signal RxWait = 2 RxIRq BitPhase RxWait = 2 Start_of_Rx IdleIRq (Receiver Start) RX_Enable (Turn Analog On) TxEOF RxPrepare RxAwaiting Receiving Idle...
  • Page 77 BC45B4523 Position CollPos Value Comment CollErr, FramingErr are set 1st bit of 1st byte 2nd bit of 1st byte CollErr is set 8th bit of 1st byte Parity of 1st byte CollErr, ParityErr are set 1st bit of 2nd byte...
  • Page 78 BC45B4523 more than 3 bytes, EMD suppression feature will not function because it is treated as normal data frame which is usually consisted of one data byte and two associated CRC. The EMD suppression is applicable for ISO14443A protocol, ISO14443B protocol, RxMultiple setting and Receive command. For some reception frame such as ATQA or part of UID in which response is less than 3 bytes and no error, received data will be passed to FIFO.
  • Page 79 BC45B4523 Default Register Address.Bit Indication/Usage Type Value Select type of analog input signal present at RX pin ByPassEnv Sector0-0x1E.2 Read/Write for extension in long range application DecoderSrc Sector0-0x1E.0 Select input signal for internal decoder Read/Write BPSKDecMeth Sector0-0x1F.7 Define the BPSK Decoding Method...
  • Page 80 BC45B4523 Command = Transceive, Transmit, Receive St_Idle Command = Receive Command = Transmit /Transceive (000) St_RxPrepare St_TxSOF (100) (001) SOF Transmitted Start_of_Rx = ‘1’ St_TxData St_RxAwaitng (010) (101) SOF Detected Data Transmitted EMD Detected TxIRq Set St_TxEOF (011) St_Receiving RxIRq Set (110) EOF Transmitted &&...
  • Page 81 BC45B4523 CRC 8-Bit When bit CRC8 (Sector0-0x22.4) is set to 1, CRC coprocessor performs 8-bit CRC calculation. The polynomial for 8-bit CRC calculation is X +1. Preset value for 8-bit CRC calculation is defined in CRCPresetMSB (Sector0-0x23). The output from CRC calculation is displayed in CRCResultMSB.
  • Page 82 BC45B4523 RxFilterTune Command Command Input Data Required Return Data Interrupt Action Code in FIFO Read from FIFO Flag Activate the filter-frequency-corner-tuning 0x10 — — IdleIRq process in receiver amplifier The RxFilterTune command activates the filter-frequency-corner-tuning process in the receiver amplifier. This command is for adjusting the filter frequency corner due to variations in temperature and manufacturing process.

  • Page 83: Circuit Configuration

    FIFO + Revision The ReadSignature command returns the BC45B4523’s device parameter and production into FIFO. Note that, MaskSet, ProductionParam and Revision can be directly read via SPI from registers at Sector1-0x0D, Sector1- 0x0E and Sector1-0x0F consecutively.
  • Page 84 100nF 100nF 10μF 10μF 100nF LAnt RSTPD BC45B4523 VMID (3.3V) 100nF MOSI MISO 27.12MHz Typical Circuit Configuration of BC45B4523 for Closed Coupling Component Example 1 Example 2 LAnt 0.4μH (Q=50) 0.4μH (Q=50) 0.47μH 0.33μH 260pF 370pF 33pF 47pF 650pF 645pF...
  • Page 85 C) Single Ended Output with matching D) Class-E Various Transmitter Configurations that BC45B4523 Supports The device is capable to receive demodulated baseband from an external envelope detector. Employing the external envelope detector can yield better sensitivity than performing through the internal one because large amount of carrier is removed, while the baseband signal is not significantly attenuated comparing to the carrier dividing scheme.

  • Page 86: Test Signals

    BC45B4523 Power Supply & Grounding In NFC systems, the receiver extracts the card-response signal from the envelope of the RF carrier on the antenna. Except for some smartcards where their operating range is deliberately limited by their designs, the noise in transmitter, which inevitably reflects back to receiver system, is a limiting factor for the reading performance, especially in ISO15693.
  • Page 87 BC45B4523 OUT3P RESET_INT OUT3P and RESET_INT (Test Register is Set to 0x10) VRECT CORR_S_VALID VRECT and CORR_S_VALID (Test Register is Set to 0x1E) Rev. 1.20 October 28, 2020...
  • Page 88 BC45B4523 VRECT CORR_S_DATA VRECT and CORR_S_DATA (Test Register is Set to 0x0E) VRECT CORR_S_COLL VRECT and CORR_S_COLL (Test Register is Set to 0x1F) For BPSK decoder in ISO14443A at higher rate and ISO14443B, the Twait must be set to assert before SOF of the card response.
  • Page 89 BC45B4523 OUT3P BPSK_DATA OUT3P and BPSK_DATA (Test Register is Set to 0x11) OUT3P S_VALID OUT3P and S_VALID (Test Register is Set to 0x12) Rev. 1.20 October 28, 2020...
  • Page 90 BC45B4523 OUT3P S_DATA OUT3P and S_DATA (Test Register is Set to 0x13) Furthermore, when the proprietary protocol is implemented, external MCU need to decode baseband itself by probling out RAW_DATA as shown in the following figures. OUT3N RAW_DATA OUT3N and RAW_DATA (Test Register is Set to 0x19) for Manchester Pattern Rev.
  • Page 91 BC45B4523 OUT3N RAW_DATA OUT3N and RAW_DATA (Test Register is Set to 0x19) for BPSK Pattern The following table summarizes key test codes for configuring the Test[6:0] bit field (Sector0-0x3A.[6:0]) to route internal key signals to monitor for adjustment of the above parameters. While the meanings of such signals are explained in the accompanying “Meaning of Key Test Signal”...

  • Page 92: Thermal Considerations

    BC45B4523 Signal Description MANCH_WO_SUB Process Manchester without subcarrier signal TX_EN Signal indicating transmitter is enabled following register configuration Meaning of Key Test Signal Thermal Considerations Silicon temperature during operation should not exceed the maximum limit at 125°C for best performance and long term reliability.
  • Page 93 BC45B4523 × (V – V ) + I × (V – V Out,Dig InReg OutReg Out,Ana InReg OutReg For example, the transmitter is designed to drive a differential antenna from a 5V power supply and deliver 250mA peak output current. Regulator supplies 150mA output current by relying on 5V input.

  • Page 94: Package Information

    BC45B4523 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information.
  • Page 95 BC45B4523 SAW Type 24-pin QFN (4mm×4mm×0.85mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. 0.031 0.033 0.035 0.000 0.001 0.002 — 0.008 BSC — 0.007 0.010 0.012 — 0.157 BSC — — 0.157 BSC — — 0.020 BSC —...
  • Page 96 However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise.

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