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IC
IDT79R3041-16J(IDT)
C-MOS RISC CPU
-TOP VIEW-
10
5
1
GND
V
DD (+ 5V )
15
20
GND
V
DD (+ 5V )
25
30
GND
V
DD (+ 5V )
35
40
PIN
PIN
I/O
SIGNAL
I/O
SIGNAL
NO.
NO.
A/D ( 23 )
1
I/O
22
-
A/D ( 24 )
2
I/O
23
I
A/D ( 25 )
3
I/O
24
I
4
I/O
A/D ( 26 )
25
I
SINT ( 2 )
-
V
SINT ( 1 )
5
26
I
DD
SINT ( 0 )
6
-
GND
27
I
A/D ( 27 )
7
I/O
28
I/O
*1/IOSTROBE
A/D ( 28 )
8
I/O
29
I/O
*2/EXTDATAEN
A/D ( 29 )
9
I/O
30
O
10
I/O
A/D ( 30 )
31
-
11
I/O
A/D ( 31 )
32
-
12
-
GND
33
O
MEMSTROBE
13
-
V
34
I
BUSREQ
DD
14
I
CLK IN
35
I
RDCEN
15
I
TRISTATE
36
I
16
O
BE16 ( 1 )
37
I
BUSERROR
17
O
BE16 ( 0 )
38
I
RESET
ADDR ( 1 )
18
O
39
O
BUSGNT
ADDR ( 0 )
19
O
40
O
SYSCLK
INT ( 5 )
20
I
41
-
21
-
GND
42
-
*1 ; SBRCOND ( 3 )
*2 ; SBRCOND ( 2 )
CLOCK
14
GENERATOR
CLK IN
UNIT
SYSTEM CONTROL
COPROCESSOR
24,23,20
EXCEPTION/CONTROL
INT3-5
REGISTERS
BUS INTERFACE
REGISTERS
PORT SIZE
REGISTER
COUNTER
30
TC
REGISTERS
32
PHYSICAL ADDRESS BUS
INSTRUCTION
CACHE
54-56,59-64,
67-72,75-80,
DATA
4-DEEP
83-4,7-11
UNPACK
WRITE
ADDRESS/
DATA 0-31
UNUT
BUFFER
R3051 SUPERSET
32
BUS INTERFACE UNIT
4-DEEP
DATA
34,39
PACK
READ
DMA CTRL
UNIT
BUFFER
45,44
RD/WR
DMA
TIMING/
CTRL
ARBITER
INTERFACE
BIU
40
CONTROL
SYS CLK
CONTROL
4-4
80
75
GND
V
DD (+ 5V )
70
V
DD (+ 5V )
GND
65
60
GND
V
DD (+ 5V )
55
45
50
( V
PIN
PIN
I/O
SIGNAL
I/O
SIGNAL
NO.
NO.
A/D ( 8 )
V
43
O
DATA EN
64
I/O
DD
INT ( 4 )
44
O
WR
65
-
INT ( 3 )
45
O
RD
66
-
46
O
ALE
67
I/O
A/D ( 9 )
LAST
I/O
A/D ( 10 )
47
O
68
A/D ( 11 )
48
O
DIAG
69
I/O
A/D ( 12 )
49
-
GND
70
I/O
A/D ( 13 )
50
-
V
71
I/O
DD
ADDR ( 2 )
A/D ( 14 )
TC
51
O
72
I/O
GND
52
O
ADDR ( 3 )
73
-
V
53
O
BURST/WRNEAR
74
-
DD
A/D ( 0 )
A/D ( 15 )
54
I/O
75
I/O
A/D ( 1 )
A/D ( 16 )
55
I/O
76
I/O
A/D ( 2 )
A/D ( 17 )
56
I/O
77
I/O
A/D ( 18 )
ACK
57
-
V
78
I/O
DD
58
-
GND
79
I/O
A/D ( 19 )
59
I/O
A/D ( 3 )
80
I/O
A/D ( 20 )
A/D ( 4 )
60
I/O
81
-
A/D ( 5 )
61
I/O
82
-
A/D ( 6 )
A/D ( 21 )
GND
62
I/O
83
I/O
A/D ( 7 )
A/D ( 22 )
V
63
I/O
84
I/O
DD
MASTER PIPELINE CONTROL
INTEGER
CPU CORE
GENERAL REGISTERS
28,29
(32×32)
2
ALU
SHIFTER
MULT/DIY UNIT
ADDRESS ADDER
PC CONTROL
VIRTUAL
ADDRESS
DATA
CACHE
32
2KB
512B
DATA BUS
INPUT
ACK
; ACKNOWLEDGE
BUSERROR
; BUS ERROR
BUSREQ
; DMA ARBITER BUS REQUEST
CLK
; MASTER CLOCK
INT ( 3 ) - ( 5 )
; PROCESSOR INTERRUPT 3-5
RDCEN
; READ BUFFER CLOCK ENABLE
RESET
; MASTER PROCESSOR RESET
SBRCOND/IO STROBE
; BRANCH CONDITION PORT
/IO STROBE
SBRCOND/EXT DATA EN
; BRANCH CONDITION PORT
/EXT DATA EN
SINT ( 0 ) - ( 2 )
; PROCESSOR INTERRUPT 0-2
TRISTATE
; TRL-STATE
OUTPUT
ADDR0-3
; LOW ADDRESS 0-3
BE16 ( 0 ) , ( 1 )
; BYTE ENABLE STROBES FOR
16-BIT MEMORY PORT 0,1
BURST/WRNEAR
; BURST TRANSFER WRITE NEAR
BUSGNT
; DMA ARBITER BUS GRANT
DATA EN
; DATA ENABLE
DIAG
; DIAGNOSTIC
LAST
; LAST DATUM IN MINI BURST
MEMSTROBE
; MEMORY STROBE
RD
; READ
SYSCLK
; SYSTEM REFERENCE CLOCK
TC
; TERMINAL COUNT
= + 5V )
DD
INPUT/OUTPUT
A/D0-31
; ADDRESS DATA 0-31
ALE
; ADDRSS LATCH ENABLE
GND
WR
; WRITE
V
DD
V
DD
GND
GND
V
DD
SBRCOND 2,3
36
19
ACK
ADDR0
18
ADDR1
37
51
BUS ERROR
ADDR2
34
52
BUS REQ
ADDR3
14
BURST/
53
WRNEAR
24
39
INT ( 3 )
BUSGNT
23
43
INT ( 4 )
DATA EN
20
INT ( 5 )
35
48
RDCEN
DIAG
38
RESET
40
SYSCLK
29
54
SBRCOND ( 2 )
A/D0
28
55
SBRCOND ( 3 )
A/D1
56
A/D2
27
59
SINT ( 0)
A/D3
26
60
SINT ( 1 )
A/D4
25
61
SINT ( 2 )
A/D5
62
A/D6
63
A/D7
64
A/D8
46
67
ALE
A/D9
68
A/D10
15
69
TRISTATE
A/D11
70
A/D12
71
A/D13
72
A/D14
75
A/D15
76
A/D16
77
A/D17
78
A/D18
79
A/D19
80
A/D20
83
A/D21
84
A/D22
1
A/D23
2
A/D24
3
A/D25
4
A/D26
17
7
BE16 ( 0 )
A/D27
16
8
BE16 ( 1 )
A/D28
30
9
TC
A/D29
10
A/D30
33
11
MEMSTO
A/D31
ROBE
44
WR
47
45
LAST
RD
CNU-500
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