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United Electronic Industries DNA-AI-208 User Manual

Strain gauge analog input layer
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DNA/DNR-AI-208
Strain Gauge Analog Input Layer
—
User Manual
18-bit, 8-channel, 4- and 6-wire Strain Gauge
Differential Input Layers
for the PowerDNA Cube and RACKtangle chassis
November 2013 Version 4.6
PN Man-DNx-AI-208-1113
© Copyright 1998-2010 United Electronic Industries, Inc. All rights reserved.
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Summary of Contents for United Electronic Industries DNA-AI-208

  • Page 1 Strain Gauge Analog Input Layer — User Manual 18-bit, 8-channel, 4- and 6-wire Strain Gauge Differential Input Layers for the PowerDNA Cube and RACKtangle chassis November 2013 Version 4.6 PN Man-DNx-AI-208-1113 © Copyright 1998-2010 United Electronic Industries, Inc. All rights reserved.
  • Page 2 COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. Products sold by United Electronic Industries, Inc. are not authorized for use as critical components in life support devices or systems. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

  • Page 3: Table Of Contents

    ..............33 © Copyright 2009 Tel::508-921-4600 www.ueidaq.com Vers: 1.8 United Electronic Industries, Inc. Date: August 2009 AI-208TOC.fm...
  • Page 4 Appendix B – Shunt Calibration ..........25 Strain Gauge Bridge ....................25 Strain Gauge with Shunt Resistance Rs Added ............26 Using Shunt Resistors on the DNA-AI-208 Layer ............28 © Copyright 2009 Tel::508-921-4600 www.ueidaq.com...

  • Page 5: Chapter 1 Introduction

    This is an alphabetical index of topics covered in this manual. NOTE: A glossary of terms used with the PowerDNA Cube and layers can be viewed and/or downloaded from www.ueidaq.com © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap1.fm...
  • Page 6 For instance, it can represent a command, as in the following exam- ple: “You can instruct users how to run setup using a command such as setup.exe.” © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap1.fm...

  • Page 7: The Dnx-Ai-208 Analog Input Layer

    DNx-AI-208 Analog Input Layer Chapter 1 Introduction This manual describes the DNA-AI-208 18-bit, 8-channel, Strain Gauge Analog Input Board/Layer. It also describes the DNA-STP-208 Screw Terminal Panel DNx-AI-208 accessory board. The technical specifications for the DNA/DNR-AI-208 Analog Analog Input Input Layer are listed in Table 1-1.

  • Page 8: Device Architecture

    Layer Position Jumpers DB-37 (female) 37-pin I/O connectors Figure 1-1. Photos of DNR and DNA-AI-208 Boards Device The DNA/DNR-AI-208 Analog Input Layer board has eight individual analog Architecture input channels. A Block Diagram of the board/layer is shown in Figure 1-2.

  • Page 9: Connectors

    When using a long cable to a sensor, be sure to use the same gauge wire for the excitation source, GND, and GND Sense lines. © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap1.fm...

  • Page 10: Analog Input Ground Connections

    AGND to the ground of the signal source and eliminate the resistors shown in Figure 1-4 for floating differential input signals. © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap1.fm...

  • Page 11: Chapter 2 Programming With The High Level Api

    (acquired voltage divided by actual excitation voltage), as follows: © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap2.fm...

  • Page 12: Configuring The Timing

    However, you can also clean up the session manually (to reuse the the Session object with a different set of channels or parameters). session.CleanUp(); © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap2.fm...

  • Page 13: Chapter 3 Programming With The Low-Level Api

    If you’d like to select the CL clock from an external clock source such as the SYNCx line, set DQ_LN_CLCKSRC1 as well. Aggregate rate = Per-channel rate * Number of channels © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap3.fm...

  • Page 14: Channel List Settings

    CL update frequency – 10Hz. You can reprogram the update frequency by calling the DqCmdSetClk() command after the first call to DqAdv208Read(). © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap3.fm...
  • Page 15 : measure shunt resistor Rb DQL_IOCTL208_READ_Rb : measure S+ to S- DQL_IOCTL208_READ_SS : measure P+ to AGND DQL_IOCTL208_READ_PP : measure PS+ to AGND DQL_IOCTL208_READ_PS © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap3.fm...

  • Page 16: Using Layer In Acb Mode

    #define CFG208 (DQ_LN_ENABLED \ |DQ_LN_ACTIVE \ |DQ_LN_CLCKSRC0 \ |DQ_LN_RAW32) uint32 Config = CFG208; STEP 1: Start DQE engine. #ifndef _WIN32 DqInitDAQLib(); #endif © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap3.fm...
  • Page 17 // We will not use event notification at first - just retrieve scans while (keep_looping) { DqeWaitForEvent(&bcb, 1, FALSE, EVENT_TIMEOUT, &events); if (events & DQ_eFrameDone) { minrq = acb.framesize; © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap3.fm...

  • Page 18: Using Layer In Dmap Mode

    DqStartDQEngine(1000*10, &pDqe, NULL); // open communication with IOM hd0 = DqOpenIOM(IOM_IPADDR0, DQ_UDP_DAQ_PORT, TIMEOUT_DELAY, &DQRdCfg); // Receive IOM crucial identification data DqCmdEcho(hd0, DQRdCfg); © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap3.fm...
  • Page 19 ", *(uint32*)ioffset[i]); STEP 6: Stop operation. DqeEnable(FALSE, &pBcb, 1, FALSE); STEP 7: Clean up. DqDmapDestroy(pBcb); DqStopDQEngine(pDqe); DqCloseIOM(hd0); #ifndef _WIN32 DqCleanUpDAQLib(); #endif © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap3.fm...
  • Page 20 DNx-AI-208 Analog Input Layer Chapter 3 Programming with the Low-Level API © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI208 Chap3.fm...

  • Page 21: Appendix A - Accessories

    Since the panel is supplied with a DB-37 board-mounted connector that mates directly with the I/O connector on a DNA-AI-208 Layer board, it can be plugged directly into the Layer in the Cube. As an alternative, you can use a DNA-CBL-37 37-way Flat Ribbon Cable or a DNA-CBL-37S 37-way Round Cable to mount the unit as a desktop panel.
  • Page 22 The Bridge Completion Resistors in the table are shown in the bridge circuit wir- ing diagrams illustrated in Figure A-4 and Figure A-5. © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App A.fm...

  • Page 23: Pinout Diagram For The Dna-Stp-Ai-208

    6-wire Circuit. Insert jumper when using a 4-wire connection. Remove when using a 6-wire connection. Figure A-3. Single-Channel Wiring Diagram — Full-Bridge © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App A.fm...

  • Page 24: Single-Channel Wiring Diagram - Half-Bridge

    SOT23 onto board or connected package, soldered to screw terminals.) to board.) Figure A-4. Single-Channel Wiring Diagram — Half-Bridge © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App A.fm...

  • Page 25: Single-Channel Wiring Diagram - Quarter-Bridge

    SOT23 onto board or connected package, soldered to screw terminals.) to board.) Figure A-5 Single-Channel Wiring Diagram — Quarter-Bridge © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App A.fm...

  • Page 26: Physical Layout Of Stp-Ai-208 Board

    SOT23 divider Ch.1 AGND Solder terminals for bridge completion resistors Ground for connector shield Figure A-6. Physical Layout of STP-AI-208 Board © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App A.fm...

  • Page 27: Other Accessories

    AI-208 layer. Accessories DNA-CBL-37 3ft, 37-way flat ribbon cable; connects DNA-AI-208 to panels. DNA-CBL-37S 3ft, 37-way round extender cable with thumbscrew connectors on both ends; connects DNA-AI-208 to screw termination panels and other devices DNA-STP-37 37-way screw terminal panel.

  • Page 28: Appendix B - Shunt Calibration

    Vout is the output voltage measured by the instrument. The formula to calculate Vout, knowing Vex, is:   Eq. 1: Vout -------------------- - – -------------------- -   © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App B.fm...
  • Page 29 Standard values for Rg are 120, 350, and 1000 Ohms. After setting R1= R2= R3=Rg, Equation 3 becomes:   ΔVout Eq. 4: -------------------------- - -Vex   © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App B.fm...
  • Page 30 Factor: ΔVoutCalculated Eq. 6: ---------------------------------------- - ΔVoutMeasured Multiplying each measured values by the “Gain Adjustment Factor” gives us cal- ibrated measurements. © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App B.fm...

  • Page 31: Using Shunt Resistors On The Ai-208

    5k 0.1% P– Figure B-3. Using Shunt Resistors on the DNA-AI-208 Layer The internal circuitry of the AI-208 makes it difficult to know the exact value of the resistance used to shunt the Wheatstone bridge, due to the following factors: •...
  • Page 32 Eq. 4 or 5. Calculate Gain Adjustment Fac- Disengage shunt calibration resistors and apply adjustment factor to every measurement from now on. © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App B.fm...

  • Page 33: Shunt Calibration In C

    // Assume all gauge resistances are 330 Ohms double Rgage = 330; // calculate actual and theoretical offset caused by shunt. © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App B.fm...

  • Page 34: Shunt Calibration In Labview

    The procedure is as follows: STEP 1: Create a session to measure voltage with excitation. STEP 2: Measure bridge output without shunt. © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App B.fm...
  • Page 35 STEP 3: Measure bridge output with shunt enabled. STEP 4: Calculate Gain Adjustment Factor. STEP 5: Apply Gain Adjustment Factor to measurements. © Copyright 2009 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File: AI-208 App B.fm...

  • Page 36: Index

    Gain(s) Single-channel Wiring Ground Connections 21, 22 SOT23 Specifications Half-bridge Strain Gauge Strain Gage Input Mode Wiring Diagram — Half- Bridge Wiring Settings Differential © Copyright 2007 Tel: 508-921-4600 www.ueidaq.com Vers: 4.6 United Electronic Industries, Inc. Date: November 2013 File:AI-208IX.fm...

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