United Electronic Industries DN-SL-514 Series User Manual

Synchronous serial interface board with differential inputs/outputs for the powerdna cube and rack series chassis

Advertisement

Quick Links

DNx-SL-514
User Manual
Synchronous Serial Interface Board
with Differential Inputs/Outputs for the
PowerDNA Cube and RACK Series Chassis
May 2018
PN Man-DNx-SL-514
© Copyright 1998-2018 United Electronic Industries, Inc. All rights reserved.

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the DN-SL-514 Series and is the answer not in the manual?

Questions and answers

Summary of Contents for United Electronic Industries DN-SL-514 Series

  • Page 1 DNx-SL-514 — User Manual Synchronous Serial Interface Board with Differential Inputs/Outputs for the PowerDNA Cube and RACK Series Chassis May 2018 PN Man-DNx-SL-514 © Copyright 1998-2018 United Electronic Industries, Inc. All rights reserved.
  • Page 2 COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. Products sold by United Electronic Industries, Inc. are not authorized for use as critical components in life support devices or systems. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
  • Page 3: Table Of Contents

    Writing Slave Data for Transmit ........24 May 2018 www.ueidaq.com © Copyright 2018 United Electronic Industries, Inc. 508.921.4600...
  • Page 4 Reading Status ..........25 May 2018 www.ueidaq.com © Copyright 2018 United Electronic Industries, Inc. 508.921.4600...
  • Page 5 Photo of DNA-SL-514 Synchronous Serial Board ............6 Block Diagram of SL-514....................7 SSI Transmission Waveform ..................8 Example of Debouncing and Tv time Delays..............9 Settable Termination Circuit Diagram................11 Pinout Diagram of the SL-514 Board................12 May 2018 www.ueidaq.com © Copyright 2018 United Electronic Industries, Inc. 508.921.4600...
  • Page 6: Chapter 1 Introduction

    The index provides an alphabetical listing of the topics covered in this manual. NOTE: A glossary of terms used with the PowerDNA Cube/RACK and I/O boards can be viewed or downloaded from www.ueidaq.com. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 7 PowerDNR RACKtangle rack mounted system, whichever is applicable. The term DNR is a specific reference to the RACKtangle, DNA to the PowerDNA I/O Cube, and DNx to refer to both. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 8: Sl-514 Board Overview

    Software included with the DNx-SL-514 provides a comprehensive yet easy to 1.2.5 Software use API that supports all popular operating systems including Windows, Linux, Support real-time operating systems such as QNX, RTX, VxWorks and more. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 9: Features

    Debouncing/glitch removal on clock and data (when debouncing is • enabled, the maximum baud rate is restricted to 1.65 Mbaud) Protection 7 kV ESD, 350V isolation • Power consumption 2W • © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 10: Specification

    5 g (rms), 10-500 Hz, broad-band random IEC 60068-2-27 Shock 50 g, 3 ms half sine, 18 shocks @ 6 orientations 30 g, 11 ms half sine, 18 shocks @ 6 orientations MTBF 350,000 hours © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 11: Indicators

    • running in point-by-point mode) ON: Operation mode • DNA bus connector RDY LED STS LED DB-37 (female) 37-pin I/O connector Figure 1-1 Photo of DNA-SL-514 Synchronous Serial Board © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 12: Device Architecture

    (DATAOUT pin), MSB first. The data word consists of a user-programmed number of bits, from 3 to 32 bits. Refer to Figure 1-3. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 13: Ssi Transmission Waveform

    A slave defect protocol error will occur if the master clock is not high for the full t period (clock high is too short vs the programmed value). © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 14: Serial Port Configuration Options

    FIFO buffer, or wait for a global trigger. Timestamps. Master ports can latch a timestamp to be stored with each received serial data word (up to 1024 serial data words and 1024 accompanying timestamps). © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 15: Fifo Operation & Timestamping

    Data storage for each slave controller is provided by a 1024 x 32-bit FIFO. Users can store up to 1024 words in the slave output FIFO at a time. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 16: Error Checking & Status Reporting

    The SL-514 is compliant with RS-422 and RS-485 standards for electrical 1.7.6 Electrical characteristics of drivers and receivers used in serial communication. Specification for Serial Port Refer to TIA/EIA-422 and TIA/EIA-485 Standards documentation for more information. Lines © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 17: Wiring & Connectors (Pinout)

    All signals are referenced relative to isolated ground (iGND). NOTE: If you are using a accessory panel with the SL-514, please refer to the Appendix for a description of the panel. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 18: Chapter 2 Programming With The High-Level Api

    The Session object controls all operations on your PowerDNx device. Therefore, Creating a the first task is to create a session object: Session // create a session object for input, and a session object for output CUeiSession ssiSession; © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 19: Configuring The Resource String

    Bit Update Time: Specifies the time (t ) in microseconds from the rising • clock edge to the data in transitioning high to low or low to high (double) © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 20: Configuring An Ssi Slave Port

    Bit Update Time: Specifies the time (t ) in microseconds from the rising • clock edge to the data out transitioning high to low or low to high (double) © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 21: Configuring Minimum Pulse Widths

    1 to 50 ns and the slave port on channel 2 to 100 ns: // Set minimum pulse width parameters masterMPW = dynamic_cast<CUeiSSIMasterPort*>(ssiSession.GetChannel(1)); masterMPW->SetMinimumDataPulseWidth(0.050); slaveMPW = dynamic_cast<CUeiSSISlavePort*>(ssiSession.GetChannel(2)); slaveMPW->SetMinimumClockPulseWidth(0.100); © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 22: Configuring The Timing

    // Enable timestamping on port 0 (channel0) if not already enabled CUeiSSIMasterPort* master0; bool TSenabled; master0 = dynamic_cast<CUeiSSIMasterPort*>(ssiSession.GetChannel(0)); TSenabled = master0->IsTimestampingEnabled(); if(!TSenabled) master0->EnableTimestamping(true); NOTE: When reading data, the timestamp is read directly following the data word. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 23: Reading Data

    To reuse the object with a different set of channels or parameters, the Session you can manually clean up the session as follows: // clean up the sessions ssiSession.CleanUp(); © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 24: Chapter 3 Programming With The Low-Level Api

    PLL source is selected. The default clock source for baud rate programming is the 66 MHz clock, not the PLL. Reads error states/status states DqAdv514Status © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 25: Low-Level Programming Techniques

    Code examples specifically for the SL-514 have 514 specified in the name, (i.e., Sample514.c). SL-514 can be operated using the immediate (point-to-point) data acquisition protocol. Sample514.c provides an example of acquiring data using this mode. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 26: Configuring Serial Interface

    // Tp, master uint32 s_Tm; // Tm, master } L514_CONFIG, *pL514_CONFIG; Table 3-2 lists configuration options for each element. All parameters listed in Table 3-2 are uint32. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 27 • 0=bypass • 1 thru 15 = 4 thru 18, 15 ns clocks,  (i.e., programming a “1” results in 4*15ns, or ~60 ns debouncing delay) © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 28: Setting The Baud Rate Using The Pll

    PLL. The PLL dividers may not be able to produce the exact programmed rate; in which case, the value closest to the user-programmed rate is used. Users can check the actual_baud parameter to know what baud rate is used. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 29: Enabling Ssi Channels

    // Pointer to the array of transmit data int* written, // Number of data words stored in FIFO int* available); // Amount of free space in FIFO © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 30 11 for additional descriptions of error conditions and status bits. Status bits are returned as type pL514_STATUS. The pL514_STATUS structure consists of two elements: // SSI channel status © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 31 • 1= receiving data SL514_CSTS_TXFHF (1L<<1) Slave TX is below watermark: • 1= below watermark SL514_CSTS_RXFHF (1L<<0) Master RX is above watermark: • 1= above watermark Status Bit Meanings Table 3-3 SL-514 © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 32 29 10 30 11 31 12 32 13 33 14 34 15 35 16 36 17 37 18 CABLE SHIELD to JP2 to JP3 DNA-STP-37D 37-way direct-connect screw terminal panel. © Copyright 2018 May 2018 www.ueidaq.com United Electronic Industries, Inc. 508.921.4600...
  • Page 33 Support FTP Site High Level API //ftp.ueidaq.com ii Support Web Site Jumper Settings www.ueidaq.com Tel: 508-921-4600 May 2018 www.ueidaq.com www.ueidaq.com Vers: 4.5 © Copyright 2018 © Copyright 2018 United Electronic Industries, Inc. United Electronic Industries, Inc. Date: 05. 10. 2018 DNx-SL-514-ManualIX.fm 508.921.4600...

This manual is also suitable for:

Dna-sl-514Dnr-sl-514Dnf-sl-514

Table of Contents